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| 1 for more information www.linear.com/LTC6811-1 typical application features description multicell battery monitors the ltc ? 6811 is a multicell battery stack monitor that measures up to 12 series connected battery cells with a total measurement error of less than 1.2mv. the cell measurement range of 0v to 5v makes the ltc6811 suitable for most battery chemistries. all 12 cells can be measured in 290s, and lower data acquisition rates can be selected for high noise reduction. multiple ltc6811 devices can be connected in series, per - mitting simultaneous cell monitoring of long, high voltage batter y strings. each ltc6811 has an isospi interface for high speed, rf-immune, long distance communications. using the LTC6811-1, multiple devices are connected in a daisy chain with one host processor connection for all devices. using the ltc6811 -2, multiple devices are con - nected in parallel to the host processor, with each device individually addressed. the ltc6811 can be powered directly from the battery stack or from an isolated supply. the ltc6811 includes passive balancing for each cell, with individual pwm duty cycle control for each cell. other features include an onboard 5v regulator, five general purpose i/o lines and a sleep mode, where current consumption is reduced to 4a. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and isospi is a trademark of analog devices, inc. all other trademarks are the property of their respective owners. patents 8908779, 9182428, 9270133. n pin-compatible upgrade from the ltc6804 n measures up to 12 battery cells in series n 1.2mv maximum total measurement error n stackable architecture supports 100s of cells n built-in isospi tm interface n 1mb isolated serial communications n uses a single twisted pair, up to 100 meters n low emi susceptibility and emissions n 290s to measure all cells in a system n synchronized voltage and current measurement n 16-bit delta-sigma adc with programmable 3rd order noise filter n engineered for iso 26262-compliant systems n passive cell balancing with programmable timer n 5 general purpose digital i/o or analog inputs n temperature or other sensor inputs n configurable as an i 2 c or spi master n 4a sleep mode supply current n 48-lead ssop package applications n electric and hybrid electric vehicles n backup battery systems n grid energy storage n high power portable equipment ltc6811 16 + ? adc data i/o iso26262 diagnostics voltage reference sensors 68111 ta01a mux switch on/off measurement error (mv) 2.0 1.5 0.5 ?0.5 ?1.5 1.0 0.0 ?1.0 ?2.0 real world cell measurement budget additional pcb assembly shift cell = 3.3v measurement error, 25c additional change ?40c to 125c 68111 ta01b lt c6811-1/lt c6811-2 68111fb
2 for more information www.linear.com/LTC6811-1 table of contents features ............................................................................................................................ 1 applications ....................................................................................................................... 1 t ypical application ............................................................................................................... 1 description ......................................................................................................................... 1 absolute maximum ratings ..................................................................................................... 3 pin configuration ................................................................................................................. 3 order information ................................................................................................................. 4 electrical characteristics ........................................................................................................ 4 t ypical performance characteristics ......................................................................................... 10 pin functions ..................................................................................................................... 16 block diagram .................................................................................................................... 17 differences between the ltc6804 and the ltc6811 ....................................................................... 19 operation ..........................................................................................................................20 state diagram ....................................................................................................................................................... 20 core ltc6811 state descriptions ......................................................................................................................... 20 isospi state descriptions ..................................................................................................................................... 21 power consumption ............................................................................................................................... .............. 21 adc operation ............................................................................................................................... ....................... 21 data acquisition system diagnostics ................................................................................................................... 28 w atchdog and discharge timer ............................................................................................................................ 34 s pin pulse width modulation for cell balancing .................................................................................................. 35 i 2 c/spi master on ltc6811 using gpios............................................................................................................. 36 s pin pulsing using the s control register group ................................................................................................ 40 serial inter face overview ............................................................................................................................... ....... 41 4-wire serial peripheral interface (spi) physical layer ........................................................................................ 41 2-wire isolated inter face (isospi) physical layer ................................................................................................. 42 data link layer ..................................................................................................................................................... 49 network layer ....................................................................................................................................................... 50 applications information ....................................................................................................... 64 providing dc power ............................................................................................................................... ............... 64 internal protection and filtering ............................................................................................................................ 66 cell balancing ....................................................................................................................................................... 68 discharge control during cell measurements ...................................................................................................... 70 digital communications ........................................................................................................................................ 72 enhanced applications .......................................................................................................................................... 82 reading external t emperature probes .................................................................................................................. 85 package description ............................................................................................................ 86 revision history ................................................................................................................. 87 t ypical application .............................................................................................................. 88 related parts ..................................................................................................................... 88 lt c6811-1/lt c6811-2 68111fb 3 for more information www.linear.com/LTC6811-1 absolute maximum ratings total supply voltage, v + to v C ................................... 75v s upply voltage (relative to c6 ), v + to c6 .................. 5 0v input voltage (relative to v C ), c0 ......................................................... C 0. 3v to 0.3v c12 .............................. C 0. 3v to min(v + + 5.5v , 75v ) c(n) ...................................... C 0. 3v to min(8 ? n, 75v ) s(n) ...................................... C 0. 3v to min(8 ? n, 75v ) ipa, ima, ipb, imb ............ C 0.3 v to v reg + 0.3v , 6v drive ...................................................... C 0.3 v to 7v all other pins ........................................... C 0.3 v to 6v voltage between inputs c(n) to c(n C 1) ........................................ C 0. 3v to 8v s(n) to c(n C 1) ........................................ C 0. 3v to 8v c12 to c9 ............................................... C 0. 3v to 21v (note 1) pin configuration LTC6811-1 ltc6811-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view g package 48-lead plastic ssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc)* sdi (nc)* sck (ipa)* csb (ima)* isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? ** gpio3 gpio2 gpio1 c0 s1 t jmax = 150c, ja = 55c/w *the function of these pins depends on the connection of isomd isomd tied to v C : csb, sck, sdi, sdo isomd tied to v reg : ima, ipa, nc, nc **this pin must be connected to v C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 top view g package 48-lead plastic ssop 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias)* sdi (icmp)* sck (ipa)* csb (ima)* isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? ** gpio3 gpio2 gpio1 c0 s1 t jmax = 150c, ja = 55c/w *the function of these pins depends on the connection of isomd isomd tied to v C : csb, sck, sdi, sdo isomd tied to v reg : ima, ipa, nc, nc **this pin must be connected to v C c9 to c6 ................................................. C 0. 3v to 21v c6 to c3 ................................................. C 0. 3v to 21v c3 to c0 ................................................. C 0. 3v to 21v current in/out of pins all pins except v reg , ipa, ima, ipb, imb, s(n) .. 10m a ipa, ima, ipb, imb ............................................. 30m a operating temperature range lt c 6811 i .............................................. C 40 c to 85 c lt c 6811 h .......................................... C 40 c to 125 c specified temperature range lt c 6811 i .............................................. C 40 c to 85 c lt c 6811 h .......................................... C 40 c to 125 c junction temperature ........................................... 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature (soldering 10 sec) .................... 30 0 c lt c6811-1/lt c6811-2 68111fb 4 for more information www.linear.com/LTC6811-1 order information tube tape and reel part marking* package description specified temperature range ltc6811ig-1#pbf ltc6811ig-1#trpbf ltc6811g-1 48-lead plastic ssop C40c to 85c ltc6811hg-1#pbf ltc6811hg-1#trpbf ltc6811g-1 48-lead plastic ssop C40c to 125c ltc6811ig-2#pbf ltc6811ig-2#trpbf ltc6811g-2 48-lead plastic ssop C40c to 85c ltc6811hg-2#pbf ltc6811hg-2#trpbf ltc6811g-2 48-lead plastic ssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container . parts ending with pbf are rohs and weee compliant. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. electrical characteristics symbol parameter conditions min typ max units adc dc specifications measurement resolution l 0.1 mv/bit adc offset voltage (note 2) l 0.1 mv adc gain error (note 2) l 0.01 0.02 % % t otal measurement error (tme) in normal mode c(n) to c(n C 1), gpio(n) to v C ?=?0 0.2 mv c(n) to c(n C 1)?=?2.0 0.1 0.8 mv c(n) to c(n C 1), gpio(n) to v C ?=?2.0 l 1.4 mv c(n) to c(n C 1)?=?3.3 0.2 1.2 mv c(n) to c(n C 1), gpio(n) to v C ?=?3.3 l 2.2 mv c(n) to c(n C 1)?=?4.2 0.3 1.6 mv c(n) to c(n C 1), gpio(n) to v C ?=?4.2 l 2.8 mv c(n) to c(n C 1), gpio(n) to v C ?=?5.0 1 mv sum of cells l 0.05 0.25 % internal temperature, t?=?maximum specified temperature 5 c v reg pin l 0.1 0.25 % v ref2 pin l 0.02 0.1 % digital supply voltage v regd l 0.1 1 % the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. the isomd pin is tied to the v C pin, unless otherwise noted. http://www.linear.com/product/LTC6811-1#orderinfo lt c6811-1/lt c6811-2 68111fb 5 for more information www.linear.com/LTC6811-1 electrical characteristics symbol parameter conditions min typ max units total measurement error (tme) in filtered mode c(n) to c(n C 1), gpio(n) to v C ?=?0 0.1 mv c(n) to c(n C 1)?=? 2.0 0.1 0.8 mv c(n) to c(n C 1), gpio(n) to v C ?=?2.0 l 1.4 mv c(n) to c(n C 1)?=? 3.3 0.2 1.2 mv c(n) to c(n C 1), gpio(n) to v C ?=?3.3 l 2.2 mv c(n) to c(n C 1) ?=?4.2 0.3 1.6 mv c(n) to c(n C 1), gpio(n) to v C ?=?4.2 l 2.8 mv c(n) to c(n C 1), gpio(n) to v C ?=?5.0 1 mv sum of cells l 0.05 0.25 % internal temperature, t?=?maximum specified temperature 5 c v reg pin l 0.1 0.25 % v ref2 pin l 0.02 0.1 % digital supply voltage v regd l 0.1 1 % total measurement error (tme) in fast mode c(n) to c(n C 1), gpio(n) to v C ?=?0 2 mv c(n) to c(n C 1), gpio(n) to v C ?=?2.0 l 4 mv c(n) to c(n C 1), gpio(n) to v C ?=?3.3 l 4.7 mv c(n) to c(n C 1), gpio(n) to v C ?=?4.2 l 8.3 mv c(n) to c(n C 1), gpio(n) to v C ?=?5.0 10 mv sum of cells l 0.15 0.5 % internal temperature, t?=?maximum specified temperature 5 c v reg pin l 0.3 1 % v ref2 pin l 0.1 0.25 % digital supply voltage v regd l 0.2 2 % input range c(n), n?=?1 to 12 l c(n C 1) c(n?C ?1)?+?5 v c0 l 0 gpio(n), n?=?1 to 5 l 0 5 v i l input leakage current when inputs are not being measured (state: core = standby) c(n), n?=?0 to 12 l 10 250 na gpio(n), n?=?1 to 5 l 10 250 na input current when inputs are being measured (state: core = measure) c(n), n?=?0 to 12 1 a gpio(n), n?=?1 to 5 1 a input current during open wire detection l 70 100 130 a voltage reference specifications v ref1 1 st reference voltage v ref1 pin, no load l 3.1 3.2 3.3 v 1 st reference voltage tc v ref1 pin, no load 3 ppm/c 1 st reference voltage hysteresis v ref1 pin, no load 20 ppm 1 st reference v. long term drift v ref1 pin, no load 20 ppm/ khr the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. the isomd pin is tied to the v C pin, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 6 for more information www.linear.com/LTC6811-1 electrical characteristics symbol parameter conditions min typ max units v ref2 2 nd reference voltage v ref2 pin, no load l 2.995 3 3.005 v v ref2 pin, 5k load to v C l 2.995 3 3.005 v 2 nd reference voltage tc v ref2 pin, no load 10 ppm/c 2 nd reference voltage hysteresis v ref2 pin, no load 100 ppm 2 nd reference v. long term drift v ref2 pin, no load 60 ppm/ khr general dc specifications i vp v + supply current (see figure?1: ltc6811 operation state diagram) state: core?=?sleep, isospi?=?idle v reg ?=?0v 4.1 7 a v reg ?=?0v l 4.1 10 a v reg ?=?5v 1.9 3 a v reg ?=?5v l 1.9 5 a state: core?=?standby l 8 6 13 13 19 24 a a state : core?=?refup or measure l 0.4 0.375 0.55 0.55 0.75 0.775 ma ma i reg(core) v reg supply current (see figure?1: ltc6811 operation state diagram) state: core?=?sleep, isospi?=?idle v reg ?=?5v 2.2 4 a v reg ?=?5v l 2.2 6 a state: core?=?standby l 17 14 40 40 67 70 a a state : core?=?refup l 0.2 0.15 0.45 0.45 0.7 0.75 ma ma state : core?=?measure l 10.8 10.7 11.5 11.5 12.2 12.3 ma ma i reg(isospi) additional v reg supply current if isospi in ready/active states note: active state current assumes t clk ?=?1s. (note 3) ltc6811-2, isomd?=?1 r b1 + r b2 ?=?2k ready l 3.6 4.5 5.4 ma active l 4.6 5.8 7.0 ma LTC6811-1, isomd?=?0 r b1 + r b2 ?=?2k ready l 3.6 4.5 5.2 ma active l 5.6 6.8 8.1 ma LTC6811-1, isomd?=?1 r b1 + r b2 ?=?2k ready l 4.0 5.2 6.5 ma active l 7.0 8.5 10.5 ma ltc6811-2, isomd?=?1 r b1 + r b2 ?=?20k ready l 1.0 1.8 2.6 ma active l 1.2 2.2 3.2 ma LTC6811-1, isomd?=?0 r b1 + r b2 ?=?20k ready l 1.0 1.8 2.4 ma active l 1.3 2.3 3.3 ma LTC6811-1, isomd?=?1 r b1 + r b2 ?=?20k ready l 1.6 2.5 3.5 ma active l 1.8 3.1 4.8 ma v + supply voltage tme specifications met l 11 40 55 v v + to c12 voltage tme specifications met l C0.3 v v + to c6 voltage tme specifications met l 40 v v reg v reg supply voltage tme supply rejection < 1mv/v l 4.5 5 5.5 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. the isomd pin is tied to the v C pin, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 7 for more information www.linear.com/LTC6811-1 electrical characteristics symbol parameter conditions min typ max units drive output voltage sourcing 1a l 5.4 5.2 5.7 5.7 5.9 6.1 v v sour cing 500a l 5.1 5.7 6.1 v v regd digital supply voltage l 2.7 3 3.6 v discharge switch on resistance v cell ?=?3.6v l 10 25 thermal shutdown temperature 150 c v ol(wdt) watch dog timer pin low wdt pin sinking 4ma l 0.4 v v ol(gpio) general purpose i/o pin low gpio pin sinking 4ma (used as digital output) l 0.4 v adc timing specifications t cycle (figure?3, figure?4, figure?6) measurement + calibration cycle t ime when starting from the refup state in normal mode measure 12 cells l 2120 2335 2480 s measure 2 cells l 365 405 430 s measure 12 cells and 2 gpio inputs l 2845 3133 3325 s measurement + calibration cycle time when starting from the refup state in filtered mode measure 12 cells l 183 201.3 213.5 ms measure 2 cells l 30.54 33.6 35.64 ms measure 12 cells and 2 gpio inputs l 244 268.4 284.7 ms measurement + calibration cycle time when starting from the refup state in fast mode measure 12 cells l 1010 1113 1185 s measure 2 cells l 180 201 215 s measure 12 cells and 2 gpio inputs l 1420 1564 1660 s t skew1 (figure?6) skew t ime. the t ime difference between cell 12 and gpio1 measurements, command?=?adcvax fast mode l 176 194 206 s normal mode l 493 543 576 s t skew2 (figure?3) skew t ime. the t ime difference between cell?12 and cell?1 measurements, command?=?adcv fast mode l 211 233 248 s normal mode l 609 670 711 s t wake regulator startup time v reg generated from drive pin (figure?32) l 200 400 s t sleep (figure?1) watchdog or discharge timer dten pin?=?0 or dcto[3:0]?=?0000 l 1.8 2 2.2 sec dten pin?=?1 and dcto[3:0] 0000 0.5 120 min t refup (figure?3 for example) reference w ake-up t ime. added to t cycle time when starting from the standby state. t refup ?=?0 when starting from other states. t refup is independent of the number of channels measured and the adc mode. l 2.7 3.5 4.4 ms f s adc clock frequency 3.3 mhz spi interface dc specifications v ih(spi) spi pin digital input voltage high pins csb, sck, sdi l 2.3 v v il(spi) spi pin digital input voltage low pins csb, sck, sdi l 0.8 v v ih(cfg) configuration pin digital input voltage high pins isomd, dten, gpio1 to gpio5, a0 to a3 l 2.7 v v il(cfg) configuration pin digital input voltage low pins isomd, dten, gpio1 to gpio5, a0 to a3 l 1.2 v i leak(dig) digital input current pins csb, sck, sdi, isomd, dten, a0 to a3 l 1 a v ol(sdo) digital output low pin sdo sinking 1ma l 0.3 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. the isomd pin is tied to the v C pin, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 8 for more information www.linear.com/LTC6811-1 electrical characteristics symbol parameter conditions min typ max units isospi dc specifications (see figure?17) v bias voltage on ibias pin ready/active state idle state l 1.9 2.0 0 2.1 v v i b isolated interface bias current r bias ?=?2k to 20k l 0.1 1.0 ma a ib isolated interface current gain v a 1.6v i b ?=?1ma i b ?=?0.1ma l l 18 18 20 20 22 24.5 ma/ma ma/ma v a transmitter pulse amplitude v a ?=?|v ip Cv im | l 1.6 v v icmp threshold-setting voltage on icmp pin v tcmp ?=?a tcmp ? v icmp l 0.2 1.5 v i leak(icmp) input leakage current on icmp pin v icmp ?=?0v to v reg l 1 a i leak(ip/im) leakage current on ip and im pins idle state, v ip or v im , 0v to v reg l 1 a a tcmp receiver comparator threshold voltage gain v cm ?=?v reg /2 to v reg C 0.2v, v icmp ?=?0.2v to 1.5v l 0.4 0.5 0.6 v/v v cm receiver common mode bias ip/im not driving (v reg C v icmp /3 C 167mv) v r in receiver input resistance single-ended to ipa, ima, ipb, imb l 26 35 45 k isospi idle/wake-up specifications (see figure?26) v wake differential wake-up voltage t dwell ?=?240ns l 200 mv t dwell dwell time at v wake before wake detection v wake ?=?200mv l 240 ns t ready startup time after wake detection l 10 s t idle idle timeout duration l 4.3 5.5 6.7 ms isospi pulse timing specifications (see figure?24) t ?pw(cs) chip-select half-pulse width transmitter l 120 150 180 ns t filt(cs) chip-select signal filter receiver l 70 90 110 ns t inv(cs) chip-select pulse inversion delay transmitter l 120 155 190 ns t wndw(cs) chip-select valid pulse window receiver l 220 270 330 ns t ?pw(d) data half-pulse width transmitter l 40 50 60 ns t filt(d) data signal filter receiver l 10 25 35 ns t inv(d) data pulse inversion delay transmitter l 40 55 65 ns t wndw(d) data valid pulse window receiver l 70 90 110 ns spi timing requirements (see figure?16 and figure?25) t clk sck period (note 4) l 1 s t 1 sdi setup time before sck rising edge l 25 ns t 2 sdi hold time after sck rising edge l 25 ns t 3 sck low t clk ?=?t 3 + t 4 1s l 200 ns t 4 sck high t clk ?=?t 3 + t 4 1s l 200 ns t 5 csb rising edge to csb falling edge l 0.65 s t 6 sck rising edge to csb rising edge (note 4) l 0.8 s t 7 csb falling edge to sck rising edge (note 4) l 1 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. the isomd pin is tied to the v C pin, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 9 for more information www.linear.com/LTC6811-1 electrical characteristics symbol parameter conditions min typ max units isospi timing specifications (see figure?25) t 8 sck falling edge to sdo valid (note 5) l 60 ns t 9 sck rising edge to short 1 transmit l 50 ns t 10 csb transition to long 1 transmit l 60 ns t 11 csb rising edge to sdo rising (note 5) l 200 ns t rtn data return delay l 325 375 425 ns t dsy(cs) chip-select daisy-chain delay l 120 180 ns t dsy(d) data daisy-chain delay l 200 250 300 ns t lag data daisy-chain lag (vs. chip-select) =? [t dsy(d) + t ?pw(d) ] C [t dsy(cs) + t ?pw(cs) ] l 0 35 70 ns t 5(gov) chip-select high-to-low pulse governor l 0.6 0.82 s t 6(gov) data to chip-select pulse governor l 0.8 1.05 s note 1: stresses beyond those listed under the absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the adc specifications are guaranteed by the total measurement error specification. note 3: the active state current is calculated from dc measurements. the active state current is the additional average supply current into v reg when there is continuous 1mhz communications on the isospi ports with 50% data 1s and 50% data 0s. slower clock rates reduce the supply current. see applications information section for additional details. note 4: these timing specifications are dependent on the delay through the cable, and include allowances for 50ns of delay each direction. 50ns corresponds to 10m of cat5 cable (which has a velocity of propagation of 66% the speed of light). use of longer cables would require derating these specs by the amount of additional delay. note 5: these specifications do not include rise or fall time of sdo. while fall time (typically 5ns due to the internal pull-down transistor) is not a concern, rising-edge transition time t rise is dependent on the pull-up resistance and load capacitance on the sdo pin. the time constant must be chosen such that sdo meets the setup time requirements of the mcu. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. the test conditions are v + = 39.6v, v reg = 5.0v unless otherwise noted. the isomd pin is tied to the v C pin, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 10 for more information www.linear.com/LTC6811-1 typical performance characteristics measurement error vs temperature measurement error due to ir reflow measurement error long-term drift measurement error vs input, normal mode measurement error vs input, filtered mode measurement error vs input, fast mode measurement noise vs input, normal mode measurement noise vs input, filtered mode measurement noise vs input, fast mode t a = 25c, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 75 10 adc measurements averaged at each input input (v) 0 1 2 3 4 5 ?10 100 ?8 ?6 ?4 ?2 0 2 4 6 8 10 125 measurement error (mv) 68111 g06 input (v) 0 1 2 3 4 5 0 ?2.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?1.5 peak noise (mv) 68111 g07 input (v) 0 1 2 3 4 5 0 ?1.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?0.5 peak noise (mv) 68111 g08 input (v) 0 1 2 3 4 5 0 0 1 2 3 4 5 6 7 8 9 10 0.5 peak noise (mv) 68111 g09 1.0 cell voltage = 3.3v 1.5 2.0 measurement error (mv) 68111 g01 change in gain error (ppm) ?100 ?60 ?20 20 60 5 typical units 100 140 0 1 2 3 4 5 6 7 temperature (c) number of parts 68111 g02 cell voltage = 3.3v 7 typical parts time (hours) 0 500 1000 1500 2000 ?50 2500 ?32 ?25 ?18 ?10 ?3 4 12 measurement error (ppm) 68111 g03 ?25 10 adc measurements averaged at each input input (v) 0 1 2 3 4 5 ?2.0 0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 measurement error (mv) 68111 g04 25 10 adc measurements averaged at each input input (v) 0 1 2 3 4 5 ?2.0 50 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 measurement error (mv) 68111 g05 11 for more information www.linear.com/LTC6811-1 typical performance characteristics measurement gain error hysteresis, hot measurement gain error hysteresis, cold noise filter response measurement error vs v reg measurement error vs v + top cell measurement error vs v + measurement error vs common mode voltage measurement error due to a v reg ac disturbance measurement error due to a v + ac disturbance t a = 25c, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 80 30 35 40 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 100 1.5 2.0 measurement error (mv) 68111 g14 c12?c11 = 3.3v c12 = 39.6v v + (v) 36 38 40 0 42 44 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 10 2.0 top cell measurement error (mv) 68111 g15 c12 ? c11 = 3.3v v + = 43.3v c11 voltage (v) 0 5 10 15 20 20 25 30 35 40 ?2.0 ?1.5 ?1.0 ?0.5 0 30 0.5 1.0 1.5 2.0 cell12 measurement error (mv) 68111 g16 v reg(dc) = 5v v reg(ac) = 0.5v p?p 1bit change < ?70db frequency (hz) 40 100 1k 10k 100k 1m 10m ?80 ?70 ?60 ?50 50 ?40 ?30 ?20 ?10 0 psrr (db) 68111 g17 v + dc = 39.6v v + ac = 5v p?p 1bit change < ?90db number of parts v reg generated from drive pin, figure 28 frequency (hz) 100 1k 10k 100k 1m 10m ?100 68111 g10 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 t a = 85c to 25c t a = ?40c to 25c psrr (db) 68111 g18 change in gain error (ppm) ?75 ?50 ?25 0 25 50 75 0 change in gain error (ppm) 5 10 15 20 25 30 35 40 45 number of parts ?40 68111 g11 input frequency (hz) 10 100 1k 10k 100k 1m ?70 ?60 ?20 ?50 ?40 ?30 ?20 ?10 0 noise rejection (db) 68111 g12 26hz 2khz 0 14khz 422hz 3khz 27khz 1khz 7khz v in = 2v v in = 3.3v v in = 4.2v v reg (v) 4.5 4.6 20 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 ?2.0 40 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 measurement error (mv) 68111 g13 60 measurement error of cell1 with 3.3v input v reg generated from drive pin, figure 28 v + (v) 5 10 15 20 25 12 for more information www.linear.com/LTC6811-1 typical performance characteristics measurement error cmrr vs frequency cell measurement error vs input rc values gpio measurement error vs input rc values measurement time vs temperature sleep supply current vs v + standby supply current vs v + refup supply current vs v + measure supply current vs v + v ref1 vs temperature 100nf 10nf 1f t a = 25c, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 10m 45 55 65 75 40 45 50 55 60 65 ?100 70 75 80 standby supply current (a) 68111 g24 standby supply current = v + current + v reg current 125c 85c 25c ?90 ?40c v + (v) 5 15 25 35 45 55 65 75 ?80 850 875 900 925 950 975 1000 refup supply current (a) 68111 g25 refup supply current = ?70 v + current + v reg current measure supply current = v + current + v reg current 125c 85c 25c ?40c v + (v) 5 15 ?60 25 35 45 55 65 75 10.0 10.5 11.0 11.5 ?50 12.0 12.5 13.0 measure supply current (ma) 68111 g26 5 typical units temperature (c) ?50 ?25 0 ?40 25 50 75 100 125 3.135 3.140 3.145 3.150 3.155 ?30 3.160 3.165 3.170 3.175 v ref1 (v) 68111 g27 time between measurements > 3rc c = 0 c = 100nf c = 1f ?20 c = 10f input resistance, r () 1 10 100 1k 10k 100k ?20 ?16 v cm(in) = 5v p-p ?10 ?12 ?8 ?4 0 4 8 12 16 20 gpio measurement error (mv) 0 68111 g21 rejection (db) 68111 g19 input resistance, r () 100 1k 10k ?10 ?9 normal mode conversions ?6 ?5 ?8 ?7 ?4 ?3 ?2 ?1 0 1 frequency (hz) 2 cell measurement error (mv) 68111 g20 12 cell normal mode conversions v reg = 4.5v v reg = 5v v reg = 5.5v 100 temperature (c) ?50 ?25 0 25 50 75 100 125 2.10 1k 2.15 2.20 2.25 2.30 2.35 2.40 measurement time (ms) 68111 g22 sleep supply current = v + current + v reg current 10k 125c 85c 25c ?40c v + (v) 5 15 25 35 45 100k 55 65 75 2 3 4 5 6 7 sleep supply current (a) 1m 68111 g23 125c 85c 25c ?40c v + (v) 5 15 25 35 13 for more information www.linear.com/LTC6811-1 typical performance characteristics v ref2 vs temperature v ref2 v reg line regulation v ref2 v + line regulation v ref2 load regulation v ref2 long-term drift v ref2 hysteresis, hot v ref2 hysteresis, cold v ref2 change due to ir reflow v drive vs temperature t a = 25c, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 125 100 change in v ref2 (ppm) 68111 g32 t a = 85c to 25c change in v ref2 (ppm) ?50 ?25 0 25 50 2.995 75 100 125 0 5 10 15 20 25 30 2.996 number of parts 68111 g33 t a = ?40c to 25c change in v ref2 (ppm) ?75 ?50 ?25 0 25 50 2.997 75 100 0 10 20 30 40 50 60 70 2.998 number of parts 68111 g34 change in v ref2 (ppm) ?175 ?125 ?75 ?25 25 75 125 2.999 0 1 2 3 4 5 number of parts 68111 g35 5 typical units no load 3.000 temperature (c) ?50 ?25 0 25 50 75 100 125 5.2 3.001 5.3 5.4 5.5 5.6 5.7 5.8 v drive (v) 68111 g36 3.002 5 typical units 3.003 3.004 3.005 v ref2 (v) 68111 g28 i l = 0.6ma 125c 85c 25c ?40c temperature (c) v reg (v) 4.5 4.75 5 5.25 5.5 ?200 ?130 ?60 10 ?50 80 150 change in v ref2 (ppm) 68111 g29 v reg generated from drive pin, figure 28 125c 85c 25c ?40c ?25 v + (v) 5 15 25 35 45 55 65 75 ?100 0 ?80 ?60 ?40 ?20 0 20 40 60 80 100 25 change in v ref2 (ppm) 68111 g30 v + = 39.6v v reg = 5v 125c 85c 25c ?40c i out (ma) 0.01 50 0.1 1 10 ?1000 ?800 ?600 ?400 ?200 0 200 75 change in v ref2 (ppm) 68111 g31 8 typical parts time (hours) 0 500 1000 1500 2000 2500 14 for more information www.linear.com/LTC6811-1 typical performance characteristics v drive v + line regulation v drive load regulation discharge switch on-resistance vs cell voltage internal die temperature increase vs discharge current internal die temperature measurement error vs temperature v ref1 and v ref2 power-up v reg and v drive power-up isospi current (ready) vs temperature isospi current (active) vs isospi clock frequency t a = 25c, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 35 40 45 50 increase in die temperature (c) 68111 g40 5 typical units temperature (c) ?50 ?25 0 45 25 50 75 100 125 ?10 ?8 ?6 ?4 ?2 55 0 2 4 6 8 10 temperature measurement error (c) 68111 g41 v ref1 : c l = 1f v ref2 : c l = 1f, r l = 5k 65 v ref1 v ref2 cs 0.5ms/div v ref1 1v/div v ref2 1v/div cs 5v/div 75 68111 g42 v reg : c l = 1f v reg generated from drive pin v reg v drive cs 50.0s/div v drive 2v/div ?10 v reg 2v/div cs 5v/div 68111 g43 i b = 1ma ltc6811?2, isomd=v reg ltc6811?1, isomd=v reg ltc6811?1, isomd=v? temperature (c) ?5 ?50 ?25 0 25 50 75 100 125 3.5 4.0 0 4.5 5.0 5.5 6.0 isospi current (ma) 68111 g44 isomd = v reg i b = 1ma ltc6811?1, read ltc6811?1, write 5 ltc6811?2, read ltc6811?2, write isospi clock frequency (khz) 0 200 400 600 800 1000 2 10 3 4 5 6 7 8 9 isospi current 68111 g45 125c 15 20 25 change in v drive (mv) 68111 g37 v + = 39.6v 125c 85c 25c ?40c 85c i out (ma) 0.01 0.1 1 ?100 ?90 ?80 ?70 ?60 ?50 25c ?40 ?30 ?20 ?10 0 change in v drive (mv) 68111 g38 on-resistance of internal discharge switch measured between s(n) and c(n) ?40c 125c 85c 25c ?40c cell voltage (v) 1 1.4 1.7 2.1 2.4 v + (v) 2.8 3.1 3.5 3.8 4.2 4.5 0 5 10 15 5 20 25 30 35 40 45 50 discharge switch on-resistance () 68111 g39 1 cell dischargin 15 6 cell dischargin 12 cell discharging internal discharge current (ma/cell) 0 10 20 30 40 50 60 25 70 80 0 5 10 15 20 25 30 35 15 for more information www.linear.com/LTC6811-1 typical performance characteristics ibias voltage vs temperature ibias voltage load regulation isospi driver current gain (port a/port b) vs ibias current isospi driver current gain (port a/port b) vs temperature isospi driver common mode voltage (port a/port b) vs pulse amplitude isospi comparator threshold gain (port a/port b) vs receiver common mode isospi comparator threshold gain (port a/port b) vs icmp voltage isospi comparator threshold gain (port a/port b) vs temperature typical wake-up pulse amplitude (port a) vs dwell time t a = 25c, unless otherwise noted. lt c6811-1/lt c6811-2 68111fb 75 0.48 0.50 0.52 0.54 0.56 comparator threshold gain, a tcmp (v/v) 68111 g51 3 parts icmp voltage (v) 0 100 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.44 0.46 125 0.48 0.50 0.52 0.54 0.56 comparator threshold gain, a tcmp (v/v) 68111 g52 v icmp = 0.2v v icmp = 1v temperature (c) 1.98 ?50 ?25 0 25 50 75 100 125 0.44 0.46 1.99 0.48 0.50 0.52 0.54 0.56 comparator threshold gain, a tcmp (v/v) 68111 g53 guaranteed wake?up region 2.00 wake?up dwell time, t dwell (ns) 0 100 200 300 400 500 600 2.01 0 50 100 150 200 250 300 wake?up pulse amplitude, v wake (mv) 68111 g54 2.02 ibias pin voltage (v) 68111 g46 i b = 1ma ibias current, i b (a) 0 200 400 600 800 1000 1.990 1.995 2.000 3 parts 2.005 2.010 ibias pin voltage (v) 68111 g47 v a = 1.6v v a = 1.0v v a = 0.5v ibias current, i b (a) 0 200 temperature (c) 400 600 800 1000 18 19 20 21 22 23 ?50 current gain, a ib (ma) 68111 g48 i b = 100a i b = 1ma temperature (c) ?50 ?25 0 25 50 ?25 75 100 125 18 19 20 21 22 23 current gain, a ib (ma/ma) 0 68111 g49 i b = 100a i b = 1ma pulse amplitude, v a (v) 0 0.5 1 1.5 2 2.5 25 3.0 3.5 4.0 4.5 5.0 5.5 driver common mode (v) 68111 g50 v icmp = 0.2v v icmp = 1v 50 receiver common mode, v cm (v) 2.5 3 3.5 4 4.5 5 5.5 0.44 0.46 16 for more information www.linear.com/LTC6811-1 pin functions c0 to c12: cell inputs. s1 to s12 : balance inputs/outputs. 12 internal n-mosfets are connected between s(n) and c(n C 1) for discharging cells. v + : positive supply pin. v C : negative supply pins. the v C pins must be shorted together, external to the ic. v ref2 : buffered 2 nd reference voltage for driving multiple 10k thermistors. bypass with an external 1f capacitor. v ref1 : adc reference voltage. bypass with an external 1f capacitor. no dc loads allowed. gpio[1:5]: general purpose i/o. can be used as digital inputs or digital outputs, or as analog inputs with a mea - surement range from v C to 5v . gpio[3:5] can be used as an i 2 c or spi port. dten: discharge timer enable. connect this pin to v reg to enable the discharge timer. drive: connect the base of an npn to this pin. connect the collector to v + and the emitter to v reg . v reg : 5v regulator input. bypass with an external 1f capacitor. isomd: serial interface mode. connecting isomd to v reg configures pins 41 to 44 of the ltc6811 for 2-wire isolated interface (isospi) mode. connecting isomd to v C configures the ltc6811 for 4-wire spi mode. wdt: watchdog timer output pin. this is an open drain nmos digital output. it can be left unconnected or con - nected with a 1m resistor to v reg . if the ltc6811 does not receive a valid command within 2 seconds, the watchdog timer circuit will reset the ltc6811 and the wdt pin will go high impedance. serial port pins LTC6811-1 (daisy-chainable) lt c6811-2 (addressable) isomd = v reg isomd = v C isomd = v reg isomd = v C port b (pins 45 to 48) ipb ipb a3 a3 imb imb a2 a2 icmp icmp a1 a1 ibias ibias a0 a0 port a (pins 41 to 44) (nc) sdo ibias sdo (nc) sdi icmp sdi i pa sck i pa sck ima csb ima csb csb, sck, sdi, sdo: 4- wire serial peripheral interface (spi). active low chip select (csb), serial clock (sck) and serial data in (sdi) are digital inputs. serial data out (sdo) is an open drain nmos output pin. sdo requires a 5k pull-up resistor. a0 to a3: address pins. these digital inputs are connected to v reg or v C to set the chip address for addressable se - rial commands. ip a, ima : isolated 2- wire serial interface port a. ipa (plus) and ima (minus) are a differential input/output pair. ipb, imb: isolated 2- wire serial interface port b. ipb (plus) and imb (minus) are a differential input/output pair. ibias: isolated interface current bias. tie ibias to v C through a resistor divider to set the interface output current level. when the isospi interface is enabled, the ibias pin voltage is 2v . the ipa/ima or ipb/imb output current drive is set to 20 times the current, i b , sourced from the ibias pin. icmp: isolated interface comparator voltage threshold set. tie this pin to the resistor divider between ibias and v C to set the voltage threshold of the isospi receiver comparators. the comparator thresholds are set to half the voltage on the icmp pin. lt c6811-1/lt c6811-2 68111fb 17 for more information www.linear.com/LTC6811-1 block diagram c12 c11 c10 c9 c8 c7 c0 c5 c6 c4 c3 c2 c1 ? + 68111 bd1 ipb p imb icmp ibias sdo/(nc) sdi/(nc) sck/(ipa) csb/(ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? * gpio3 gpio2 gpio1 c0 s1 v + c12 s12 c11 m s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 logic and memory digital filters serial i/o port b 6-cell mux v regd sc v reg p m aux mux 12 balance fets s(n) c(n ? 1) p m 7-cell mux por v regd v reg serial i/o port a discharge timer die temperature 2nd reference 1st reference regulators adc2 ? + adc1 16 16 v + ldo1 v regd por v + ldo2 drive 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LTC6811-1 lt c6811-1/lt c6811-2 68111fb 18 for more information www.linear.com/LTC6811-1 block diagram sdo/(ibias) c12 c11 c10 c9 c8 c7 c0 c5 c6 c4 c3 c2 c1 ? + 68111 bd2 a3 p a2 a1 a0 sdi/(icmp) sck/(ipa) csb/(ima) isomd wdt drive dten gpio5 gpio4 gpio3 gpio2 gpio1 c0 s1 c12 s12 c11 m s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 logic and memory digital filters serial i/o address 6-cell mux v regd sc v reg p m aux mux p m 7-cell mux por v regd v reg serial i/o port a discharge timer die temperature 2nd reference 1st reference regulators adc2 ? + adc1 v + ldo1 v regd por v + ldo2 drive v reg v ref1 v ref2 v ? v ? * v + 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 16 16 12 balance fets s(n) c(n ? 1) ltc6811-2 lt c6811-1/lt c6811-2 68111fb 19 for more information www.linear.com/LTC6811-1 differences between the ltc6804 and the ltc6811 the newer ltc6811 is pin compatible and backwards software compatible with the older ltc6804. users of the ltc6804 should review the following tables of product differences before upgrading existing designs. additional ltc6811 feature benefit relevant data sheet section(s) eight choices of adc speed vs resolution. the ltc6804 has six choices. flexibility for noise filtering. adc modes for a description and md[1,0] bits in t able?39. each discharge control pin (s pin) can have a unique duty cycle. improved cell balancing. s pin pulse width modulation for cell balancing for a description and p wmx[x] bits in table?51. measure cell 7 with both adcs simultaneously using the adol command. improved way to check that adc2 is as accurate as adc1. overlap cell measurement (adol command) sum of cells measurement has higher accuracy. improved way to check that the individual cell measurements are correct. measuring internal device parameters (adstat command) the new adcvsc command measures the sum of cells and the individual cells at the same time. reduces the influence of noise on the accuracy of the sum of cells measurement. measuring cell voltages and sum of cells (adcvsc command) auxiliary measurements are processed with 2 digital filters simultaneously. checks that the digital filters are free of faults. auxiliary (gpio) measurements with digital redundancy (adaxd command) and measuring internal device parameters with digital redundancy (adstatd command) the s pin has a stronger pmos pull-up transistor. reduces the possibility that board leakage can turn on discharge circuits. cell balancing with external transistors the 2 nd voltage reference has improved specifications. improved v ref2 specifications mean improved diagnostics for safety. accuracy check the ltc6811 supports daisy-chain polling. easier adc communications. polling methods commands to control the lt8584 active balance ic. easier to program the lt8584. s pin pulsing using the s control register group for a description and sctlx[x] bits in t able?50. ltc6811 restriction vs. ltc6804 impact relevant data sheet section(s) the abs max specifications for the c pins have changed. the abs max voltage between input pins, c(n) to c(n?C ?1), is 8v for both the ltc6804 and ltc6811. in addition, for the ltc6804, the average cell voltage between c(n) and c(n C 1) from pins c12 to c8, c8 to c4 and c4 to c0 must be less than 6.25v. for the ltc6811, the average cell voltage between c(n) and c(n C 1) from pins c12 to c9, c9 to c6, c6 to c3 and c3 to c0, must be less than 7.0v. c12 to c9, c9 to c6, c6 to c3 and c3 to c0 in absolute maximum ratings the abs max specifications for the c pins have changed. if v + is powered from a separate supply (not directly powered from the battery stack), the v + supply voltage must be less than (50v?+?c6). if v + is powered from the battery stack (ie. v + ?=?c12), this restriction has no impact since the maximum voltage between c6Cc12 is already restricted to 42v as noted above. c12 to c9, c9 to c6, c6 to c3 and c3 to c0 in absolute maximum ratings there is now an operating max voltage specification for v + to c6. if v + is powered from a separate supply (not directly powered from the battery stack), the v + supply voltage must be less than (40v?+?c6) to achieve the tme specifications listed in the electrical characteristics table. v + to c6 voltage in electrical characteristics lt c6811-1/lt c6811-2 68111fb 20 for more information www.linear.com/LTC6811-1 operation state diagram the operation of the ltc6811 is divided into two separate sections: the core circuit and the isospi circuit. both sec - tions have an independent set of operating states, as well as a shutdown timeout. core ltc6811 st ate descriptions sleep state the reference and adcs are powered down. the watchdog timer (see watchdog and discharge timer) has timed out. the discharge timer is either disabled or timed out. the supply currents are reduced to minimum levels. the isospi ports will be in the idle state. the drive pin is 0v. if a wakeup signal is received (see waking up the serial interface), the ltc6811 will enter the standby state. standby state the reference and the adcs are off. the watchdog timer and/or the discharge timer is running. the drive pin powers the v reg pin to 5v through an external transistor. (alternatively, v reg can be powered by an external supply). when a valid adc command is received or the refon bit is set to 1 in the configuration register group, the ic pauses for t refup to allow for the reference to power up and then enters either the refup or measure state. otherwise, if no valid commands are received for t sleep (when both the watchdog and discharge timer have expired), the ltc6811 returns to the sleep state. if the discharge timer is disabled, only the watchdog timer is relevant. refup state to reach this state the refon bit in the configuration register group must be set to 1 (using the wrcfga command, see table? 38). the adcs are off. the refer - ence is powered up so that the ltc6811 can initiate adc conversions more quickly than from the st andby state. when a valid adc command is received, the ic goes to the measure state to begin the conversion. otherwise, the ltc6811 will return to the standby state when the refon bit is set to 0, either manually (using wrcfga command) or automatically when the watchdog timer expires (the ltc6811 will then move straight into the sleep state if both timers are expired). measure state the ltc6811 performs adc conversions in this state. the reference and adcs are powered up. after adc conversions are complete, the ltc6811 will transition to either the refup or standby state, depend - ing on the refon bit. additional adc conversions can be initiated more quickly by setting refon? = ?1 to take advantage of the refup state. note: non-adc commands do not cause a core state tran - sition. only an adc conversion or diagnostic commands will place the core in the measure state. 68111 f01 isospi port core ltc6811 conversion done (refon = 1) wakeup signal (t wake ) adc command (t refup ) adc command refon = 1 (t refup ) wakeup signal (core = standby) (t ready ) wakeup signal (core = sleep) (t wake ) transmit/receive note: state transition delays denoted by (t x ) no activity on isospi port idle timeout (t idle ) conversion done (refon = 0) refon = 0 wd timeout (if dten = 0) or dt timeout (if dten = 1) (t sleep ) measure refup standby sleep active ready idle figure?1. ltc6811 operation state diagram lt c6811-1/lt c6811-2 68111fb 21 for more information www.linear.com/LTC6811-1 operation isospi state descriptions note: the lt c6811-1 has two isospi ports (a and b), for daisy-chain communication. the lt c6811-2 has only one isospi port (a), for parallel-addressable communication. idle state the isospi ports are powered down. when isospi port a receives a wakeup signal (see wak - ing up the serial interface), the isospi enters the ready state. this transition happens quickly (within t ready ) if the core is in the standby state because the drive and v reg pins are already biased up. if the core is in the sleep state when the isospi receives a wakeup signal, the part transitions to the ready state within t wake . ready state the isospi port(s) are ready for communication. port?b is enabled only for lt c6811 -1, and is not present on the lt c6811 -2. the serial interface current in this state depends on if the part is lt c6811 -1 or lt c6811 -2, the status of the isomd pin and r bias ?=?r b1 + r b2 (the external resistors tied to the ibias pin). if there is no activity (i.e. no wakeup signal) on port a for greater than t idle? ?= ??5.5ms, the ltc6811 goes to the idle?state. when the serial interface is transmitting or receiving data the ltc6811 goes to the active state. active state the ltc6811 is transmitting/receiving data using one or both of the isospi ports. the serial interface consumes maximum power in this state. the supply current increases with clock frequency as the density of isospi pulses increases. power consumption the ltc6811 is powered via two pins: v + and v reg . the v + input requires voltage greater than or equal to the top cell voltage minus 0.3v, and it provides power to the high voltage elements of the core circuitry. the v reg input requires 5v and provides power to the remaining core circuitry and the isospi circuitry. the v reg input can be powered through an external transistor, driven by the regulated drive output pin. alternatively, v reg can be powered by an external supply. the power consumption varies according to the operational states. table?1 and table?2 provide equations to approximate the supply pin currents in each state. the v + pin current depends only on the core state. however, the v reg pin current depends on both the core state and isospi state, and can therefore be divided into two components. the isospi interface draws current only from the v reg pin. i reg ?=?i reg(core) + i reg(isospi) table?1. core supply current state i vp i reg(core) sleep v reg ?=?0v 4.1a 0a v reg ?=?5v 1.9a 2.2a standby 13a 40a refup 550a 450a measure 550a 11.5ma in the sleep state the v reg pin will draw approximately 2.2a if powered by an external supply. otherwise, the v + pin will supply the necessary current. adc operation there are two adcs inside the ltc6811. the two adcs operate simultaneously when measuring twelve cells. only one adc is used to measure the general purpose inputs. the following discussion uses the term adc to refer to one or both adcs, depending on the operation being performed. the following discussion will refer to a dc1 and adc2 when it is necessary to distinguish between the two circuits, in timing diagrams, for example. adc modes the adcopt bit (cfg r0 [0] ) in the configuration register group and the mode selection bits md [1:0] in the conver - sion command together provide eight modes of operation for the adc, which correspond to different oversampling ratios (osr). the accuracy and timing of these modes are summarized in table?3. in each mode, the adc first mea - sures the inputs, and then performs a calibration of each channel. the names of the modes are based on the C 3db bandwidth of the adc measurement. lt c6811-1/lt c6811-2 68111fb 22 for more information www.linear.com/LTC6811-1 operation mode 7khz (normal): in this mode, the adc has high resolution and low tme (total measurement error). this is considered the normal operating mode because of the optimum combination of speed and accuracy. mode 27khz (fast): in this mode, the adc has maximum throughput but has some increase in tme (total measurement error). so this mode is also referred to as the fast mode. the increase in speed comes from a reduction in the oversampling ratio. this results in an increase in noise and average measurement error. mode 26hz (filtered): in this mode, the adc digital filter C3db frequency is lowered to 26hz by increasing the osr. this mode is also referred to as the filtered mode due to its low C3db frequency. the accuracy is similar to the 7khz (normal) mode with lower noise. table?2. isospi supply current equations isospi state device isomd connection i reg(isospi) idle LTC6811-1/ltc6811-2 n/a 0ma ready LTC6811-1 v reg 2.2ma + 3 ? i b v C 1.5ma + 3 ? i b ltc6811-2 v reg 1.5ma + 3 ? i b v C 0ma active LTC6811-1 v reg write: 2.5ma + 3 + 20 ? 100ns t clk ? ? ? ? ? ? ?i b r ead: 2.5ma + 3 + 20 ? 100ns ? 1.5 t clk ? ? ? ? ? ? ?i b v C 1.8ma + 3 + 20 ? 100ns t clk ? ? ? ? ? ? ?i b ltc6811-2 v reg write: 1.8ma + 3 ?i b r ead: 1.8ma + 3 + 20 ? 100ns ? 0.5 t clk ? ? ? ? ? ? ?i b v C 0ma note: i b = v bias /(r b1 + r b2 ) table?3. adc filter bandwidth and accuracy mode C3db filter bw C40db filter bw tme spec at 3.3v, 25c tme spec at 3.3v,C40c, 125c 27khz (fast mode) 27khz 84khz 4.7mv 4.7mv 14khz 13.5khz 42khz 4.7mv 4.7mv 7khz (normal mode) 6.8khz 21khz 1.2mv 2.2mv 3khz 3.4khz 10.5khz 1.2mv 2.2mv 2khz 1.7khz 5.3khz 1.2mv 2.2mv 1khz 845hz 2.6khz 1.2mv 2.2mv 422hz 422hz 1.3khz 1.2mv 2.2mv 26hz (filtered mode) 26hz 82hz 1.2mv 2.2mv note: tme is the total measurement error. lt c6811-1/lt c6811-2 68111fb 23 for more information www.linear.com/LTC6811-1 operation modes 14khz, 3khz, 2khz, 1khz and 422hz: modes 14khz, 3khz, 2khz, 1khz and 422hz provide ad - ditional options to set the adc digital filter C3db frequency at 13.5khz , 3.4khz, 1.7khz, 845hz and 422hz respectively. the accuracy of the 14khz mode is similar to the 27khz (fast) mode. the accuracy of 3khz, 2khz, 1khz and 422hz modes is similar to the 7khz (normal) mode. the filter bandwidths and the conversion times for these modes are provided in table?3 and table?5. if the core is in standby state, an additional t refup time is required to power up the reference before beginning the adc conver - sions. the reference can remain powered up between adc conversions if the refon bit in the configuration register group is set to 1 so the core is in refup state after a delay t refup . then, the subsequent adc commands will not have the t refup delay before beginning adc conversions. adc range and resolution the c inputs and gpio inputs have the same range and resolution. the adc inside the ltc6811 has an approxi - mate range from C0.82v to +5.73v. negative readings are rounded to 0v . the format of the data is a 16-bit unsigned integer where the lsb represents 100v. therefore, a reading of 0x80e8 (33,000 decimal) indicates a measure - ment of 3.3v. d e lta-sigma adcs have quantization noise which depends on the input voltage, especially at low oversampling ra - tios (osr), such as in fast mode. in some of the adc modes, the quantization noise increases as the input voltage approaches the upper and lower limits of the adc range. for example, the total measurement noise versus input voltage in normal and filtered modes is shown in figure?2. adc input voltage (v) 0 peak noise (mv) 1 0.1 0.9 0.7 0.5 0.3 0.8 0.6 0.4 0.2 0 2.5 4.5 1.5 3.5 68111 f02 5 2 4 1 3 0.5 normal mode filtered mode figure?2. measurement noise vs input voltage the specified range of the adc is 0v to 5v . in table?4, the precision range of the adc is arbitrarily defined as 0.5v to 4.5v. this is the range where the quantization noise is relatively constant even in the lower osr modes (see figure?2). table?4 summarizes the total noise in this range for all eight adc operating modes. also shown is the noise free resolution. for example, 14-bit noise free resolution in normal mode implies that the top 14 bits will be noise free with a dc input, but that the 15th and 16th least significant bits (lsb) will flicker. table?4. adc range and resolution mode full range 1 specified range precision range 2 lsb format max noise noise free resolution 3 27khz (fast) C0.8192v to 5.7344v 0v to 5v 0.5v to 4.5v 100v unsigned 16 bits 4mv p-p 10 bits 14khz 1mv p-p 12 bits 7khz (normal) 250v p-p 14 bits 3khz 150v p-p 14 bits 2khz 100v p-p 15 bits 1khz 100v p-p 15 bits 422hz 100v p-p 15 bits 26hz (filtered) 50v p-p 16 bits 1. negative readings are rounded to 0v. 2. precision range is the range over which the noise is less than max noise. 3. noise free resolution is a measure of the noise level within the precision range. lt c6811-1/lt c6811-2 68111fb 24 for more information www.linear.com/LTC6811-1 operation adc range vs voltage reference value typical adcs have a range which is exactly twice the value of the voltage reference, and the adc measurement error is directly proportional to the error in the voltage reference. the ltc6811 adc is not typical. the absolute value of v ref1 is trimmed up or down to compensate for gain errors in the adc. therefore, the adc total measure - ment error (tme) specifications are superior to the v ref1 specifications. for example, the 25c specification of the total measurement error when measuring 3.300v in 7khz (normal) mode is 1.2mv and the 25c specification for v ref1 is 3.200v100mv. measuring cell voltages (adcv command) the adcv command initiates the measurement of the battery cell inputs, pins c0 through c12. this command has options to select the number of channels to measure and the adc mode. see the section on commands for the adcv command format. figure? 3 illustrates the timing of the adcv command which measures all twelve cells. after the receipt of the adcv command to measure all 12 cells, a dc1 sequentially measures the bottom 6 cells. adc2 sequentially measures the top 6 cells. after the cell measurements are complete, each channel is calibrated to remove any offset errors. table?5. conversion times for adcv command measuring all 12 cells in different modes conversion times (in s) mode t 0 t 1m t 2m t 5m t 6m t 1c t 2c t 5c t 6c 27khz 0 57 103 243 290 432 568 975 1,113 14khz 0 86 162 389 465 606 742 1,149 1,288 7khz 0 144 278 680 814 1,072 1,324 2,080 2,335 3khz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033 2khz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430 1khz 0 959 1,907 4,753 5,701 5,961 6,213 6,970 7,222 422hz 0 1,890 3,769 9,407 11,287 11,547 11,799 12,555 12,807 26hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317 calibrate c8 to c7 calibrate c7 to c6 measure c12 to c11 measure c8 to c7 measure c7 to c6 adc2 serial interface t cycle t skew2 adcv + pec calibrate c2 to c1 calibrate c12 to c11 calibrate c6 to c5 calibrate c1 to c0 measure c6 to c5 measure c2 to c1 measure c1 to c0 adc1 t 0 t 1m t 2m t 6m t 5m t 1c t 2c t 5c t 6c 68111 f03 t refup figure?3. timing for adcv command measuring all 12 cells lt c6811-1/lt c6811-2 68111fb 25 for more information www.linear.com/LTC6811-1 table?6. conversion times for adcv command measuring only 2 cells in different modes conversion times (in s) mode t 0 t 1m t 1c 27khz 0 57 201 14khz 0 86 230 7khz 0 144 405 3khz 0 240 501 2khz 0 493 754 1khz 0 959 1,219 422hz 0 1,890 2,150 26hz 0 29,817 33,568 operation table?5 shows the conversion times for the adcv com - mand measuring all 12 cells. the total conversion time is given by t 6c which indicates the end of the calibration step. figure?4 illustrates the timing of the adcv command that measures only two cells. table?6 shows the conversion time for the adcv command measuring only 2 cells. t 1c indicates the total conversion time for this command. under/over voltage monitoring whenever the c inputs are measured, the results are com - pared to undervoltage and overvoltage thresholds stored in memor y. if the reading of a cell is above the overvoltage limit, a bit in memory is set as a flag. similarly, measure - ment results below the undervoltage limit cause a flag to be set. the overvoltage and under voltage thresholds are stored in the configuration register group. the flags are stored in the status register group b. auxiliary (gpio) measurements (adax command) the adax command initiates the measurement of the gpio inputs. this command has options to select which gpio input to measure (gpio1-5) and which adc mode to use. the adax command also measures the 2 nd reference. there are options in the adax command to measure each gpio and the 2 nd reference separately or to measure all five gpios and the 2 nd reference in a single command. see the section on commands for the adax command format. all auxiliary measurements are relative to the v C pin voltage. this command can be used to read external temperatures calibrate c10 to c9 measure c10 to c9 adc2 serial interface adcv + pec calibrate c4 to c3 measure c4 to c3 adc1 t 0 t 1m t 1c 68111 f04 t refup figure?4. timing for adcv command measuring 2 cells lt c6811-1/lt c6811-2 68111fb 26 for more information www.linear.com/LTC6811-1 operation by connecting temperature sensors to the gpios. these sensors can be powered from the 2 nd reference which is also measured by the adax command, resulting in precise ratiometric measurements. figure? 5 illustrates the timing of the adax command measuring all gpios and the 2 nd reference. since all six measurements are carried out on adc1 alone, the conver - sion time for the adax command is similar to the adcv command. auxiliary (gpio) measurements with digital redundancy (adaxd command) the adaxd command operates similarly to the adax command except that an additional diagnostic is per formed using digital redundancy. the analog modulator from adc1 is used to measure gpio1-5 and the 2 nd reference. this bit stream is input to the digital integration and differentiation machines for both adc1 and adc2. thus the measurement result is calculated with redundancy. at the end of each measure - ment, the two results are compared and if any mismatch occurs then a value of 0xff0 x ( 6.528v) is written to the result register. this value is outside of the clamping range of the adc and the host should identify this as a fault indication. the last four bits are used to indicate which nibble(s) of the result values did not match. result indication 0b1111_1111_0000_0xxx no fault detected in bits 15-12 0b1111_1111_0000_1xxx fault detected in bits 15-12 0b1111_1111_0000_x0xx no fault detected in bits 11-8 0b1111_1111_0000_x1xx fault detected in bits 11-8 0b1111_1111_0000_xx0x no fault detected in bits 7-4 0b1111_1111_0000_xx1x fault detected in bits 7-4 0b1111_1111_0000_xxx0 no fault detected in bits 3-0 0b1111_1111_0000_xxx1 fault detected in bits 3-0 the execution time of adax and adaxd is the same. table?7. conversion times for adax command measuring all gpios and 2 nd reference in different modes conversion times (in s) mode t 0 t 1m t 2m t 5m t 6m t 1c t 2c t 5c t 6c 27khz 0 57 103 243 290 432 568 975 1,113 14khz 0 86 162 389 465 606 742 1,149 1,288 7khz 0 144 278 680 814 1,072 1,324 2,080 2,335 3khz 0 260 511 1,262 1,512 1,770 2,022 2,778 3,033 2khz 0 493 976 2,425 2,908 3,166 3,418 4,175 4,430 1khz 0 959 1,907 4,753 5,701 5,961 6,213 6,970 7,222 422hz 0 1,890 3,769 9,407 11,287 11,547 11,799 12,555 12,807 26hz 0 29,817 59,623 149,043 178,850 182,599 186,342 197,571 201,317 adc2 serial interface t cycle t skew adax + pec calibrate gpio2 calibrate 2nd ref calibrate gpio1 measure 2nd ref measure gpio2 measure gpio1 adc1 t 0 t 1m t 2m t 6m t 5m t 1c t 2c t 5c t 6c 680412 f05 t refup figure?5. timing for adax command measuring all gpios and 2 nd reference lt c6811-1/lt c6811-2 68111fb 27 for more information www.linear.com/LTC6811-1 operation measuring cell voltages and gpios (adcvax command) the adcvax command combines twelve cell measure - ments with two gpio measurements (gpio1 and gpio2). this command simplifies the synchronization of battery cell voltage and current measurements when current sen - sors are connected to gpio1 or gpio2 inputs. figure?6 illustrates the timing of the adcvax command. see the section on commands for the adcv ax command format. the synchronization of the current and voltage measure - ments, t skew1 , in fast mode is within 194s. table?8 shows the conversion and synchronization time for the adcvax command in different modes. the total conversion time for the command is given by t 8c . table?8. conversion and synchronization times for adcvax command in different modes conversion times (in s) synchronization time (in s) mode t 0 t 1m t 2m t 3m t 4m t 5m t 6m t 7m t 8m t 8c t skew1 27khz 0 57 104 150 204 251 305 352 398 1,503 194 14khz 0 86 161 237 320 396 479 555 630 1,736 310 7khz 0 144 278 412 553 687 828 962 1,096 3,133 543 3khz 0 260 511 761 1,018 1,269 1,526 1,777 2,027 4,064 1009 2khz 0 493 976 1,459 1,949 2,432 2,923 3,406 3,888 5,925 1939 1khz 0 959 1,907 2,856 3,812 4,760 5,716 6,664 7,613 9,648 3801 422hz 0 1,890 3,769 5,648 7,535 9,415 11,301 13,181 15,060 17,096 7,525 26hz 0 29,817 59,623 89,430 119,244 149,051 178,864 208,671 238,478 268,442 119,234 calibrate measure c12 to c11 measure c11 to c10 measure c10 to c9 measure c9 to c8 measure c8 to c7 measure c7 to c6 adc2 serial interface t cycle t skew1 t skew1 adcvax + pec calibrate measure c6 to c5 measure c5 to c4 measure c4 to c3 measure gpio2 measure gpio1 measure c3 to c2 measure c2 to c1 measure c1 to c0 adc1 t 0 t 1m t 2m t 3m t 4m t 5m t 6m t 7m t 8m t 8c t refup 68111 f06 figure?6. timing of adcvax command lt c6811-1/lt c6811-2 68111fb 28 for more information www.linear.com/LTC6811-1 operation data acquisition system diagnostics the battery monitoring data acquisition system is com - prised of the multiplexers, adcs, 1 st reference, digital filters and memory. to ensure long term reliable performance there are several diagnostic commands which can be used to verify the proper operation of these circuits. measuring internal device parameters (adstat command) the adstat command is a diagnostic command that measures the following internal device parameters: sum of all cells (sc), internal die temperature (itmp), analog power supply (va) and the digital power supply (vd). these parameters are described in the section below. all the 8 adc modes described earlier are available for these conversions. see the section on commands for the adstat command format. figure?7 illustrates the timing of the adstat command measuring all 4 internal device parameters. table?9 shows the conversion time of the adstat com - mand measuring all 4 internal parameters. t 4c indicates the total conversion time for the adstat command. table?9. conversion times for adstat command measuring sc, itmp, va, vd conversion times (in s) mode t 0 t 1m t 2m t 3m t 4m t 1c t 2c t 3c t 4c 27khz 0 57 103 150 197 338 474 610 748 14khz 0 86 162 237 313 455 591 726 865 7khz 0 144 278 412 546 804 1,056 1,308 1,563 3khz 0 260 511 761 1,011 1,269 1,522 1,774 2,028 2khz 0 493 976 1,459 1,942 2,200 2,452 2,705 2,959 1khz 0 959 1,907 2,856 3,804 4,062 4,313 4,563 4,813 422hz 0 1,890 3,769 5,648 7,528 7,786 8,036 8,287 8,537 26hz 0 29,817 59,623 89,430 119,237 122,986 126,729 130,472 134,218 adc2 serial interface t cycle t skew adstat + pec calibrate itmp calibrate vd calibrate sc measure vd measure itmp measure sc adc1 t 0 t 1m t 2m t 4m t 3m t 1c t 2c t 3c t 4c 68111 f07 t refup figure?7. timing for adstat command measuring sc, itmp, va, vd lt c6811-1/lt c6811-2 68111fb 29 for more information www.linear.com/LTC6811-1 operation sum of cells measurement: the sum of all cells mea - surement is the voltage between c12 and c0 with a 20:1 attenuation. the 16- bit adc value of sum of cells mea - surement (sc) is stored in status register group?a. any potential difference between the c0 and v C pins results in an error in the sc measurement equal to this difference. from the sc value, the sum of all cell voltage measure - ments is given by: sum of all cells?=?sc ? 20 ? 100v internal die t emperature: the adstat command can measure the internal die temperature. the 16-bit adc value of the die temperature measurement (itmp) is stored in status register group a. from itmp, the actual die temperature is calculated using the expression: internal die temperature ( c) = i tmp ? 100v 7.5mv c C 273 c power supply measurements: the adstat command is also used to measure the analog power supply (v reg ) and digital power supply (v regd ). the 16-bit adc value of the analog power supply measurement (va) is stored in status register group a. the 16-bit adc value of the digital power supply measurement (vd) is stored in status register group b. from va and vd, the power supply measurements are given by: an alog power supply measurement (v reg )? = ?va ? ?? 100v digital power supply measurement (v regd )? = ?vd? ?? 100v the value of v reg is determined by external components. v reg should be between 4.5v and 5.5v to maintain ac - curacy. the value of v regd is determined by internal components. the normal range of v regd is 2.7v to 3.6v. measuring internal device parameters with digital redundancy (adstatd command) the adstatd command operates similarly to the adstat command except that an additional diagnostic is performed using digital redundancy. the analog modulator from adc1 is used to measure sum of cells, internal die temperature, analog power supply and digital power supply. this bit stream is input to the digital integration and differentiation machines for both adc1 and adc2. thus the measurement result is calcu - lated with redundancy. at the end of the measurement, the two results are compared and if any mismatch occurs then a value of 0xff0 x ( >?=?6.528v) is written to the result register. this value is outside of the clamping range of the adc and the host should identify this as a fault indication. the last four bits are used to indicate which nibble(s) of the result values did not match. result indication 0b1111_1111_0000_0xxx no fault detected in bits 15-12. 0b1111_1111_0000_1xxx fault detected in bits 15-12. 0b1111_1111_0000_x0xx no fault detected in bits 11-8. 0b1111_1111_0000_x1xx fault detected in bits 11-8. 0b1111_1111_0000_xx0x no fault detected in bits 7-4. 0b1111_1111_0000_xx1x fault detected in bits 7-4. 0b1111_1111_0000_xxx0 no fault detected in bits 3-0. 0b1111_1111_0000_xxx1 fault detected in bits 3-0. the execution time of adstat and adstatd is the same. lt c6811-1/lt c6811-2 68111fb 30 for more information www.linear.com/LTC6811-1 operation measuring cell voltages and sum of cells (adcvsc command) the adcvsc command combines twelve cell measure - ments and the measurement of sum of cells. this command simplifies the synchronization of the individual battery cell voltage and the total sum of cells measurements. figure? 8 illustrates the timing of the adcvsc command. see the section on commands for the adcvsc command format. the synchronization of the cell voltage and sum of cells measurements, t skew , in fast mode is within 159s. table?10 shows the conversion and synchronization time for the adcvsc command in different modes. the total conversion time for the command is given by t 7c . calibrate measure c12 to c11 measure c11 to c10 measure c10 to c9 measure c9 to c8 measure c8 to c7 measure c7 to c6 adc2 serial interface t cycle t skew adcvsc + pec calibrate measure c6 to c5 measure c5 to c4 measure c4 to c3 measure sc measure c3 to c2 measure c2 to c1 measure c1 to c0 adc1 t 0 t 1m t 2m t 3m t 4m t 5m t 6m t 7m t 7c t refup 68111 f08 figure?8. timing for adcvsc command measuring all 12 cells, sc table?10. conversion and synchronization times for adcvsc command in different modes conversion times (in s) synchronization time (in s) mode t 0 t 1m t 2m t 3m t 4m t 5m t 6m t 7m t 7c t skew 27khz 0 57 106 155 216 265 326 375 1,322 159 14khz 0 86 161 237 320 396 479 555 1,526 234 7khz 0 144 278 412 553 695 829 962 2,748 409 3khz 0 260 511 761 1,018 1,269 1,526 1,777 3,562 758 2khz 0 493 976 1,459 1,949 2,432 2,923 3,406 5,192 1,456 1khz 0 959 1,907 2,856 3,812 4,767 5,716 6,664 8,450 2,853 422hz 0 1,890 3,769 5,648 7,535 9,422 11,301 13,181 14,966 5,645 26hz 0 29,817 59,623 89,430 119,244 149,058 178,864 208,672 234,893 89,427 lt c6811-1/lt c6811-2 68111fb 31 for more information www.linear.com/LTC6811-1 operation overlap cell measurement (adol command) the adol command simultaneously measures cell 7 with adc1 and adc2. the host can compare the results from the two adcs against each other to look for inconsisten - cies which may indicate a fault. the result from adc2 is placed in cell v oltage register group c where the cell 7 result normally resides. the result from a dc1 is placed in cell voltage register group c where the cell 8 result normally resides. figure? 9 illustrates the timing of the adol command. see the section on commands for the adol command format. table?11 shows the conversion time for the adol command. t 1c indicates the total conversion time for this command. accuracy check measuring an independent voltage reference is the best means to verify the accuracy of a data acquisition system. the ltc6811 contains a 2 nd reference for this purpose. the adax command will initiate the measurement of the 2 nd reference. the results are placed in auxiliary register group b. the range of the result depends on the adc1 measurement accuracy and the accuracy of the 2 nd ref- erence, including thermal hysteresis and long term drift. readings outside the range 2.99v to 3.01v (final data sheet limits plus 2mv for hys and 3mv for ltd) indicate the system is out of its specified tolerance. adc2 is veri - fied by comparing it to adc1 using the adol command. mux decoder check the diagnostic command diagn ensures the proper op - eration of each multiplexer channel. the command cycles through all channels and sets the muxf ail bit to 1 in status register group b if any channel decoder fails. the muxf ail bit is set to 0 if the channel decoder passes the test. the muxfail bit is also set to 1 on power-up (por) or after a clrstat command. the diagn command takes about 400s to complete if the core is in refup state and about 4.5ms to complete if the core is in standby state. the polling methods described in the section polling methods can be used to determine the completion of the diagn command. calibrate c7 to c6 measure c7 to c6 adc2 serial interface adol + pec calibrate c7 to c6 measure c7 to c6 adc1 t 0 t 1m t 1c 68111 f09 t refup figure?9. timing for adol command measuring cell 7 with both adc1 and adc2 table?11. conversion times for adol command conversion times (in s) mode t 0 t 1m t 1c 27khz 0 57 201 14khz 0 86 230 7khz 0 144 405 3khz 0 240 501 2khz 0 493 754 1khz 0 959 1,219 422hz 0 1,890 2,150 26hz 0 29,817 33,568 lt c6811-1/lt c6811-2 68111fb 32 for more information www.linear.com/LTC6811-1 operation digital filter check the delta-sigma adc is composed of a 1-bit pulse den - sity modulator followed by a digital filter. a pulse density modulated bit stream has a higher per centage of 1s for higher analog input voltages. the digital filter converts this high frequency 1-bit stream into a single 16-bit word. this is why a delta-sigma adc is often referred to as an oversampling converter. the self test commands verify the operation of the digital filters and memory. figure? 10 illustrates the operation of the adc during self test. the output of the 1-bit pulse density modulator is replaced by a 1-bit test signal. the test signal passes through the digital filter and is con - verted to a 16-bit value. the 1-bit test signal undergoes the same digital conversion as the regular 1- bit signal from the modulator, so the conversion time for any self test command is exactly the same as the regular adc conversion command. the 16- bit adc value is stored in the same register groups as the corresponding regular adc conversion command. the test signals are designed to place alternating one-zero patterns in the registers. table?12 provides a list of the self test commands. if the digital filters and memory are working properly, then the registers will contain the values shown in table?12. for more details see the commands section. adc clear commands ltc6811 has three clear commands: clrcell, clraux and clrstat. these commands clear the registers that store all adc conversion results. the clrcell command clears cell voltage register groups a, b, c and d. all bytes in these registers are set to 0xff by clrcell command. the clraux command clears auxiliary register groups a and b. all bytes in these registers are set to 0xff by clraux command. 68111 f10 results register digital filter analog input mux test signal pulse density modulated bit stream 1 self test pattern generator 16 1-bit modulator figure?10. operation of ltc6811 adc self test table?12. self test command summary command self test option output pattern in different adc modes results register groups 27khz 14khz 7khz, 3khz, 2khz, 1khz, 422hz, 26hz cvst st[1:0]=01 0x9565 0x9553 0x9555 c1v to c12v (cva, cvb, cvc, cvd) st[1:0]=10 0x6a9a 0x6aac 0x6aaa axst st[1:0]=01 0x9565 0x9553 0x9555 g1v to g5v, ref (auxa, auxb) st[1:0]=10 0x6a9a 0x6aac 0x6aaa statst st[1:0]=01 0x9565 0x9553 0x9555 sc, itmp, va, vd (stata, statb) st[1:0]=10 0x6a9a 0x6aac 0x6aaa lt c6811-1/lt c6811-2 68111fb 33 for more information www.linear.com/LTC6811-1 operation the clrstat command clears status register groups a and b except the rev and rsvd bits in status register group b. a read back of rev will return the revision code of the part. rsvd bits always read back 0s. all ov and uv flags, muxfail bit and the thsd bit in status register group b are set to 1 by clrstat command. the thsd bit is set to 0 after rdstatb command. the registers stor - ing sc, itmp, va and vd are all set to 0x ff by clrstat command. open wire check (adow command) the adow command is used to check for any open wires between the adcs of the ltc6811 and the external cells. this command performs adc conversions on the c pin inputs identically to the adcv command, except two internal current sources sink or source current into the two c pins while they are being measured. the pull-up (pup) bit of the adow command determines whether the current sources are sinking or sourcing 100a. the following simple algorithm can be used to check for an open wire on any of the 13 c pins: 1. run the 12- cell command adow with pup? = ?1 at least twice. read the cell voltages for cells 1 through 12 once at the end and store them in array cell pu (n). 2. run the 12- cell command adow with pup? = ?0 at least twice. read the cell voltages for cells 1 through 12 once at the end and store them in array cell pd (n). 3. take the difference between the pull-up and pull-down measurements made in above steps for cells 2 to 12 : cell ? (n)?=?cell pu (n) C cell pd (n). 4. for all values of n from 1 to 11: if cell ? (n+1) < C 400mv, then c(n) is open. if cell pu (1)?= ?0.0000, then c(0) is open. if cell pd (12)?=?0.0000, then c(12) is open. the above algorithm detects open wires using normal mode conversions with as much as 10nf of capacitance remaining on the ltc6811 side of the open wire. however, if more external capacitance is on the open c pin, then the length of time that the open wire conversions are ran in steps 1 and 2 must be increased to give the 100a current sources time to create a large enough difference for the algorithm to detect an open connection. this can be ac - complished by running more than two adow commands in steps 1 and 2, or by using filtered mode conversions instead of normal mode conversions. use t able? 13 to determine how many conversions are necessary: table?13 external c pin capacitance number of adow commands required in steps 1 and 2 normal mode filtered mode 10nf 2 2 100nf 10 2 1f 100 2 c 1 + roundup(c/10nf) 2 thermal shutdown to protect the ltc6811 from overheating, there is a thermal shutdown circuit included inside the ic. if the temperature detected on the die goes above approximately 150c, the thermal shutdown circuit trips and resets the configura - tion register group and s control register group to their default states. this turns off all discharge switches. when a thermal shutdown event has occurred, the thsd bit in status register group b will go high. the clrstat command can also set the thsd bit high for diagnostic purposes. this bit is cleared when a read operation is performed on status register group b (rdstatb com - mand). the clrstat command sets the thsd bit high for diagnostic purposes but does not reset the configuration register group. revision code and reser ved bits the status register group b contains a 4-bit revision code (rev) and 2 reserved (rsvd) bits. if software detection of device revision is necessary, then contact the factory for details. otherwise the code can be ignored. in all cases, however, the values of all bits must be used when calculating the packet error code (pec) on data reads. lt c6811-1/lt c6811-2 68111fb 34 for more information www.linear.com/LTC6811-1 operation watchdog and discharge timer when there is no valid command for more than 2 seconds, the watchdog timer expires. this resets configuration register bytes cfgr0-3 in all cases. cfgr4 and cfgr5 and the s control register group are reset by the watchdog timer when the discharge timer is disabled. the wdt pin is pulled high by the external pull-up when the watchdog time elapses. the watchdog timer is always enabled and it resets after every valid command with matching com - mand pec. the discharge timer is used to keep the discharge switches turned on for programmable time duration. if the discharge timer is being used, the discharge switches are not turned off when the watchdog timer is activated. t o enable the discharge timer, connect the dten pin to v reg (figure? 11). in this configuration, the discharge switches will remain on for the programmed time dura- tion as determined by the dcto value in the configuration register group. table?14 shows the various time settings and the corresponding dcto value. table?15 summarizes the status of the configuration register group after a watchdog timer or discharge timer event. the status of the discharge timer can be determined by reading the configuration register group using the rdcfga command. the dcto value indicates the time left before the discharge timer expires as shown in table?16. table?14. dcto settings dcto 0 1 2 3 4 5 6 7 8 9 a b c d e f time (min) disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120 68111 f11 v reg dten ltc6811 dcto 0 2 discharge timer timeout dcten en rst clk 1 rst (por or wrcfga done or timeout) (por or valid command) clk osc 16hz osc 16hz wdt wdtpd wdtrst && ~dcten rst1 (resets dcto, dcc) rst2 (resets refup, gpio, vuv, vov) wdtrst watchdog timer figure?11. watchdog and discharge timer table?15 watchdog timer discharge timer dten?=?0, dcto?=?xxxx resets cfgr0-5 and sctrl when it fires disabled dten?=?1, dcto?=?0000 resets cfgr0-5 and sctrl when it fires disabled dten?=?1, dcto?!?=?0000 resets cfgr0-3 when it fires resets cfgr4-5 and sctrl when it fires lt c6811-1/lt c6811-2 68111fb 35 for more information www.linear.com/LTC6811-1 operation unlike the watchdog timer, the discharge timer does not reset when there is a valid command. the discharge timer can only be reset after a valid wrcfga (write configu - ration register group) command. there is a possibility that the discharge timer will expire in the middle of some commands. if the discharge timer activates in the middle of a wrcfga command, the configuration register group and s control register group will reset as per t able?15. however, at the end of the valid wrcfga command, the new data is copied to the configuration register group. the new configura - tion data is not lost when the discharge timer is activated. if the discharge timer activates in the middle of a rdcfga command, the configuration register group resets as per t able? 15. as a result, the read back data from bytes cfrg4 and cfrg5 could be corrupted. if the discharge timer activates in the middle of a rdsctrl command, the s control register group resets as per table?15. as a result, the read back data could be corrupted. s pin pulse width modulation for cell balancing for additional control of cell discharging, the host may configure the s pins to operate using pulse width modu - lation. while the watchdog timer is not expired, the dcc bits in the configuration register group control the s pins directly . after the watchdog timer expires, p wm operation begins and continues for the remainder of the selected discharge time or until a wake-up event occurs (and the watchdog timer is reset). during pwm operation, the dcc bits must be set to 1 for the pwm feature to operate. once pwm operation begins, the configurations in the pwm register may cause some or all s pins to be periodically de-asserted to achieve the desired duty cycle as shown in table?17. each pwm signal operates on a 30 second period. for each cycle, the duty cycle can be programmed from 0% to 100% in increments of 1/15? = ?6.67% (2 seconds). table?17. s pin pulse width modulation settings dcc bit (config register group) pwmc setting on time (seconds) off time (seconds) duty cycle (%) 0 4bxxxx 0 continuously off 0.0 1 4b1111 continuously on 0 100.0 1 4b1110 28 2 93.3 1 4b1101 26 4 86.7 1 4b1100 24 6 80.0 1 4b1011 22 8 73.3 1 4b1010 20 10 66.7 1 4b1001 18 12 60.0 1 4b1000 16 14 53.3 1 4b0111 14 16 46.7 1 4b0110 12 18 40.0 1 4b0101 10 20 33.3 1 4b0100 8 22 26.7 1 4b0011 6 24 20.0 1 4b0010 4 26 13.3 1 4b0001 2 28 6.7 1 4b0000 0 continuously off 0.0 table?16 dcto (read value) discharge time left (min) 0 disabled (or) timer has timed out 1 0 < timer 0.5 2 0.5 < timer 1 3 1 < timer 2 4 2 < timer 3 5 3 < timer 4 6 4 < timer 5 7 5 < timer 10 8 10 < timer 15 9 15 < timer 20 a 20 < timer 30 b 30 < timer 40 c 40 < timer 60 d 60 < timer 75 e 75 < timer 90 f 90 < timer 120 lt c6811-1/lt c6811-2 68111fb 36 for more information www.linear.com/LTC6811-1 operation each s pin pwm signal is sequenced at different intervals to ensure that no two pins switch on or off at the same time. the switching interval between channels is 62.5ms, and 0.75 seconds is required for all twelve pins to switch (12 ? 62.5ms). the default value of the p wm register is all 1s so that the ltc6811 will maintain backwards compatibility with the ltc6804 . upon entering sleep mode, the pwm register will be initialized to its default value. i 2 c/spi master on ltc6811 using gpios the i/o ports gpio3, gpio4 and gpio5 on LTC6811-1 and ltc6811 -2 can be used as an i 2 c or spi master port to communicate to an i 2 c or spi slave. in the case of an i 2 c master, gpio4 and gpio5 form the sda and scl ports of the i 2 c interface respectively. in the case of a spi master, gpio3, gpio4 and gpio5 become the csbm, sdiom and sckm ports of the spi interface respectively. the spi master on ltc6811 supports spi mode 3 (chpa? =?1, cpol?=?1). the gpios are open drain outputs, so an external pull-up is required on these ports to operate as an i 2 c or spi master. it is also important to write the gpio bits to 1 in the configuration register group so these ports are not pulled low internally by the device. comm register ltc6811 has a 6- byte comm register as shown in table?18. this register stores all data and control bits required for i 2 c or spi communication to a slave. the comm register contains three bytes of data dn[7:0] to be transmitted to or received from the slave device. icomn[3:0] specify control actions before transmitting/receiving each data byte. fcomn[3:0] specify control actions after transmit - ting/receiving each data byte. if the bit icomn [3] in the comm register is set to 1 the part becomes a spi master and if the bit is set to 0 the part becomes an i 2 c master. table?19 describes the valid write codes for icomn [3:0] and fcomn[3:0] and their behavior when using the part as an i 2 c master. table?18. comm register memory map register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comm0 rd/wr icom0[3] icom0[2] icom0[1] icom0[0] d0[7] d0[6] d0[5] d0[4] comm1 rd/wr d0[3] d0[2] d0[1] d0[0] fcom0[3] fcom0[2] fcom0[1] fcom0[0] comm2 rd/wr icom1[3] icom1[2] icom1[1] icom1[0] d1[7] d1[6] d1[5] d1[4] comm3 rd/wr d1[3] d1[2] d1[1] d1[0] fcom1[3] fcom1[2] fcom1[1] fcom1[0] comm4 rd/wr icom2[3] icom2[2] icom2[1] icom2[0] d2[7] d2[6] d2[5] d2[4] comm5 rd/wr d2[3] d2[2] d2[1] d2[0] fcom2[3] fcom2[2] fcom2[1] fcom2[0] table?19. write codes for icomn [3:0] and fcomn [3:0] on i 2 c master control bits code action description icomn[3:0] 0110 start generate a start signal on i 2 c port followed by data transmission 0001 stop generate a stop signal on i 2 c port 0000 blank proceed directly to data transmission on i 2 c port 0111 no transmit release sda and scl and ignore the rest of the data fcomn[3:0] 0000 master ack master generates an ack signal on ninth clock cycle 1000 master nack master generates a nack signal on ninth clock cycle 1001 master nack + stop master generates a nack signal followed by stop signal lt c6811-1/lt c6811-2 68111fb 37 for more information www.linear.com/LTC6811-1 operation table?20 describes the valid write codes for icomn [3:0] and fcomn[3:0] and their behavior when using the part as a spi master. note that only the codes listed in tables 19 and 20 are valid for icomn[3:0] and fcomn[3:0]. writing any other code that is not listed in tables 19 and 20 to icomn [3:0] and fcomn [3:0] may result in unexpected behavior on the i 2 c or spi port. comm commands three commands help accomplish i 2 c or spi commu - nication to the slave device: wrcomm, stcomm and rdcomm. wrcomm command : this command is used to write data to the comm register. this command writes 6 bytes of data to the comm register. the pec needs to be written at the end of the data. if the pec does not match, all data in the comm register is cleared to 1s when csb goes high. see the section bus protocols for more details on a write command format. stcomm command: this command initiates i 2 c/spi com- munication on the gpio ports. the comm register contains 3 bytes of data to be transmitted to the slave. during this command, the data bytes stored in the comm register are transmitted to the slave i 2 c or spi device and the data received from the i 2 c or spi device is stored in the comm register. this command uses gpio4 (sda) and gpio5 (scl) for i 2 c communication or gpio3 (csbm), gpio4 (sdiom) and gpio5 (sckm) for spi communication. the stcomm command is to be followed by 24 clock cycles for each byte of data to be transmitted to the slave device while holding csb low. for example, to transmit three bytes of data to the slave, send stcomm command and its pec followed by 72 clock cycles. pull csb high at the end of the 72 clock cycles of stcomm command. during i 2 c or spi communication, the data received from the slave device is updated in the comm register. rdcomm command: the data received from the slave device can be read back from the comm register using the rdcomm command. the command reads back six bytes of data followed by the pec. see the section bus protocols for more details on a read command format. table? 21 describes the possible read back codes for icomn[3:0] and fcomn[3:0] when using the part as an i 2 c master. dn [7:0] contains the data byte transmitted by the i 2 c slave. in case of the spi master, the read back codes for icomn[3:0] and fcomn[3:0] are always 0111 and 1111 respectively. dn [7:0] contains the data byte transmitted by the spi slave. table?20. write codes for icomn[3:0] and fcomn[3:0] on spi master control bits code action description icomn[3:0] 1000 csbm low generates a csbm low signal on spi port (gpio3) 1010 csbm falling edge drives csbm (gpio3) high, then low 1001 csbm high generates a csbm high signal on spi port (gpio3) 1111 no transmit releases the spi port and ignores the rest of the data fcomn[3:0] x000 csbm low holds csbm low at the end of byte transmission 1001 csbm high transitions csbm high at the end of byte transmission table?21. read codes for icomn [3:0] and fcomn [3:0] on i 2 c master control bits code description icomn[3:0] 0110 master generated a start signal 0001 master generated a stop signal 0000 blank, sda was held low between bytes 0111 blank, sda was held high between bytes fcomn[3:0] 0000 master generated an ack signal 0111 slave generated an ack signal 1111 slave generated a nack signal 0001 slave generated an ack signal, master generated a stop signal 1001 slave generated a nack signal, master generated a stop signal lt c6811-1/lt c6811-2 68111fb 38 for more information www.linear.com/LTC6811-1 operation figure?12 illustrates the operation of ltc6811 as an i 2 c or spi master using the gpios. any number of bytes can be transmitted to the slave in groups of 3 bytes using these commands. the gpio ports will not get reset between different stcomm commands. however, if the wait time between the commands is greater than 2s , the watchdog will time out and reset the ports to their default values. to transmit several bytes of data using an i 2 c master, a start signal is only required at the beginning of the entire data stream. a stop signal is only required at the end of the data stream. all intermediate data groups can use a blank code before the data byte and an ack/nack signal as appropriate after the data byte. sda and scl will not get reset between different stcomm commands. to transmit several bytes of data using spi master, a csbm low signal is sent at the beginning of the 1 st data byte. csbm can be held low or taken high for intermediate data groups using the appropriate code on fcomn[3:0]. a csbm high signal is sent at the end of the last byte of data. csbm, sdiom and sckm will not get reset between different stcomm commands. figure?13 shows the 24 clock cycles following stcomm command for an i 2 c master in different cases. note that if icomn[3:0] specified a stop condition, after the stop signal is sent, the sda and scl lines are held high and all data in the rest of the word is ignored. if icomn [3:0] is a no transmit, both sda and scl lines are released, and the rest of the data in the word is ignored. this is used when a particular device in the stack does not have to communicate to a slave. figure?14 shows the 24 clock cycles following stcomm command for a spi master. similar to the i 2 c master, if icomn[3:0] specified a csbm high or a no transmit condition, the csbm, sckm and sdiom lines of the spi master are released and the rest of the data in the word is ignored. 68111 f12 comm register gpio port i 2 c/spi slave port a rdcomm wrcomm stcomm LTC6811-1/ltc6811-2 figure?12. ltc6811 i 2 c/spi master using gpios sda (gpio4) 68111 f13 scl (gpio5) no transmit sda (gpio4) scl (gpio5) stop sda (gpio4) scl (gpio5) start ack sda (gpio4) scl (gpio5) start nack + stop sda (gpio4) scl (gpio5) blank nack (sck) t clk t 4 t 3 figure?13. stcomm timing diagram for an i 2 c master lt c6811-1/lt c6811-2 68111fb 39 for more information www.linear.com/LTC6811-1 operation timing specifications of i 2 c and spi master the timing of the ltc6811 i 2 c or spi master will be controlled by the timing of the communication at the ltc6811 s primary spi interface. table? 22 shows the i 2 c master timing relationship to the primary spi clock. table?23 shows the spi master timing specifications. table?22. i 2 c master timing i 2 c master parameter timing rela tionship to primar y spi interface timing specifications at t clk ?=?1s scl clock frequency 1/(2 ? t clk) max 500khz t hd ; sta t 3 min 200ns t low t clk min 1s t high t clk min 1s t su ; sta t clk + t 4 * min 1.03s t hd ; dat t 4 * min 30ns t su ; dat t 3 min 200ns t su ;sto t clk + t 4 * min 1.03s t buf 3 ? t clk min 3s * note: when using isospi, t 4 is generated internally and is a minimum of 30ns. also, t 3 ?=?t clk C t 4 . when using spi, t 3 and t 4 are the low and high times of the sck input, each with a specified minimum of 200ns. sdiom (gpio4) 68111 f14 sckm (gpio5) csbm high/no transmit csbm (gpio3) sdiom (gpio4) sckm (gpio5) csbm (gpio3) csbm low csbm low high sdiom (gpio4) sckm (gpio5) csbm (gpio3) csbm high low csbm low (sck) t clk t 4 t 3 figure?14. stcomm timing diagram for a spi master table?23. spi master timing spi master parameter timing rela tionship to primar y spi interface timing specifications at t clk ?=?1s sdiom valid to sckm rising setup t 3 min 200ns sdiom valid from sckm rising hold t clk + t 4 * min 1.03s sckm low t clk min 1s sckm high t clk min 1s sckm period (sckm_low + sckm_high) 2 ? t clk min 2s csbm pulse width 3 ? t clk min 3s sckm rising to csbm rising 5 ? t clk + t 4 * min 5.03s csbm falling to sckm falling t 3 min 200ns csbm falling to sckm rising t clk + t 3 min 1.2s sckm falling to sdiom valid master requires < t clk * note: when using isospi, t 4 is generated internally and is a minimum of 30ns. also, t 3 ?=?t clk C t 4 . when using spi, t 3 and t 4 are the low and high times of the sck input, each with a specified minimum of 200ns. lt c6811-1/lt c6811-2 68111fb 40 for more information www.linear.com/LTC6811-1 operation s pin pulsing using the s control register group the s pins of the ltc6811 can be used as a simple serial interface. this is particularly useful for controlling linear technologys lt8584 , a monolithic flyback dc/dc con - verter designed to actively balance large battery stacks. the lt8584 has several operating modes which are controlled through a serial inter face. the ltc6811 can communicate to an lt8584 by sending a sequence of pulses on each s pin to select a specific lt8584 mode. the s control register group is used to specify the behavior for each of the 12 s pins, where each nibble specifies whether the s pin should drive high, drive low, or send a pulse sequence of between 1 and 7 pulses. table?24 shows the possible s pin behaviors that can be sent to the lt8584. the s pin pulses occur at a pulse rate of 6.44khz (155s period). the pulse width will be 77.6s. the s pin pulsing begins when the stsctrl command is sent, after the last command pec clock, provided that the command pec matches. the host may then continue to clock sck in order to poll the status of the pulsing. this polling works similarly to the adc polling feature. the data out will remain logic low until the s pin pulsing sequence has completed. while the s pin pulsing is in progress, new stsctrl or wrsctrl commands are ignored. the pladc command may be used to determine when the s pin pulsing has completed. if the wrsctrl command and command pec are re - ceived correctly but the data pec does not match, then the s control register group will be cleared. if a dcc bit in the configuration register group is asserted, the ltc6811 will drive the selected s pin low, regardless of the s control register group. the host should leave the dcc bits set to 0 when using the s control register group. the clrsctrl command can be used to quickly reset the s control register group to all 0s and force the pulsing machine to release control of the s pins. this command may be helpful in reducing the diagnostic control loop time in an automotive application. table?24 nibble value s pin behavior 0000 0001 0010 0011 0100 0101 0110 0111 1xxx lt c6811-1/lt c6811-2 68111fb 41 for more information www.linear.com/LTC6811-1 operation serial interface overview there are two types of serial ports on the ltc6811: a standard 4- wire serial peripheral interface (spi) and a 2- wire isolated interface (isospi). the state of the isomd pin determines whether pins 41 through 44 are a 2-wire or 4-wire serial port. there are two versions of the ic: the LTC6811-1 and the ltc6811-2. the LTC6811-1 is used in a daisy-chain con - figuration and the ltc6811 -2 is used in an addressable bus configuration. the ltc6811 -1 provides a second isospi interface using pins 45 through 48. the ltc6811-2 uses pins 45 through 48 to set the address of the device, by tying these pins to v C or v reg . 4-wire serial peripheral interface (spi) physical layer external connections connecting isomd to v C configures serial port a for 4-wire spi. the sdo pin is an open drain output which requires a pull-up resistor tied to the appropriate supply voltage (figure?15). timing the 4- wire serial port is configured to operate in a spi system using cpha? = ?1 and cpol? = ?1. consequently, data on sdi must be stable during the rising edge of sck. the timing is depicted in figure?16. the maximum data rate is 1mbps. daisy-chain support 68111 f15 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 miso mosi clk cs v dd mpu ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 address pins 5k 5k v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 miso mosi clk cs v dd mpu a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6811-2 figure?15. 4-wire spi configuration lt c6811-1/lt c6811-2 68111fb 42 for more information www.linear.com/LTC6811-1 operation 2-wire isolated interface (isospi) physical layer the 2- wire interface provides a means to interconnect ltc6811 devices using simple twisted pair cabling. the interface is designed for low packet error rates when the cabling is subjected to high rf fields. isolation is achieved through an external transformer. standard spi signals are encoded into differential pulses. the strength of the transmission pulse and the threshold level of the receiver are set by two external resistors. the values of the resistors allow the user to trade off power dissipation for noise immunity. figure?17 illustrates how the isospi circuit operates. a 2v reference drives the ibias pin. external resistors r b1 and r b2 create the reference current i b . this current sets the drive strength of the transmitter. r b1 and r b2 also form a voltage divider to supply a fraction of the 2v reference for the icmp pin, which sets the threshold voltage of the receiver circuit. 68111 f16 sdi sck d3 d2 d1 d0 d7?d4 d3 current command previous command t 7 t 8 t 6 t 5 sdo csb d3 d4 d2 d1 d0 d7?d4 d3 t 1 t 2 t 3 t 4 figure?16. timing diagram of 4-wire serial peripheral interface 68111 f17 im r m ibias i b r b1 icmp 2v ip logic and memory tx = +1 tx ? 20 ? i b tx = ?1 sdo tx = 0 pulse encoder/ decoder sdi sck csb wakeup circuit (on port a) ltc6811 + ? ? + ? ? rx = +1 rx = ?1 rx = 0 r b2 comparator threshold = r b1 + r b2 1v ? r b2 0.5x figure?17. isospi interface lt c6811-1/lt c6811-2 68111fb 43 for more information www.linear.com/LTC6811-1 operation external connections the ltc6811 -1 has two serial ports which are called port?b and port a. port b is always configured as a 2-wire inter - face (master). port a is either a 2-wire or 4- wire interface (slave), depending on the connection of the isomd pin. figure?18 is an example of a robust inter connection of multiple identical pcbs, each containing one LTC6811-1. the microprocessor is located on a separate pcb. to achieve 2- wire isolation between the microprocessor pcb and the 1 st ltc6811 -1 pcb, use the ltc6820 support ic. the ltc6820 is functionally equivalent to the diagram in figure?17. the final LTC6811-1 in the daisy chain does not use port b; however, the r m should still be present. the ltc6811 -2 has a single serial port (port a) which can be 2- wire or 4-wire, depending on the state of the isomd pin. when configured for 2-wire communications, several devices can be connected in a multi-drop configuration as shown in figure?19. the ltc6820 ic is used to interface the mpu (master) to the ltc6811-2s (slaves). using a single ltc6811 when only one ltc6811 is needed, the ltc6811-2 is rec - ommended. it does not have isospi port b, so it requires fewer external components and consumes less power, especially when port a is configured as a 4- wire interface. however, the LTC6811-1 can be used as a single (non daisy-chained) device if the second isospi port (port b) is properly biased and terminated, as shown in figures?20 and 22. icmp should not be tied to gnd, but can be tied directly to ibias. a bias resistance (2k to 20k) is required for ibias. do not tie ibias directly to v reg or v C . finally, ipb and imb should be terminated into a 100 resistor (not tied to v reg or v C ). selecting bias resistors the adjustable signal amplitude allows the system to trade power consumption for communication robustness, and the adjustable comparator threshold allows the system to account for signal losses. the isospi transmitter drive current and comparator volt - age threshold are set by a resistor divider (r bias ?=?r b1 + r b2 ) between ibias and v C . the divided voltage is connected to the icmp pin, which sets the comparator threshold to ? of this voltage (v icmp ). when either isospi interface is enabled (not idle) ibias is held at 2v , causing a current i b to flow out of the ibias pin. the ip and im pin drive currents are 20 ? i b . as an example, if divider resistor r b1 is 2.8k and resistor r b2 is 1.21k (so that r bias ?=?4k), then: i b = 2v r b1 + r b2 = 0.5ma i drv ?=?i ip ?=?i im ?=?20 ? i b ?=?10ma v icmp = 2v ? r b2 r b1 + r b2 = i b ? r b2 = 603mv v tcmp ?=?0.5 ? v icmp ?=?302mv in this example, the pulse drive current i drv will be 10ma and the receiver comparators will detect pulses with ip-im amplitudes greater than 302mv. if the isolation barrier uses 1:1 transformers connected by a twisted pair and terminated with 120 resistors on each end, then the transmitted differential signal amplitude () will be: v a = i drv ? r m 2 = 0.6v (this result ignores transformer and cable losses, which may reduce the amplitude). lt c6811-1/lt c6811-2 68111fb 44 for more information www.linear.com/LTC6811-1 operation 68111 f18 vcc vcco mosi miso sck cs en slow mstr pol pha ibias icmp gnd ip im miso mosi clk cs v dd mpu ltc6820 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure?18. transformer-isolated daisy-chain configuration using LTC6811-1 68111 f19 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6811-2 address = 0x0 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6811-2 address = 0x1 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6811-2 address = 0x2 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo (ibias) sdi (icmp) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6811-2 address = 0x3 ? ? ? ? ? ? ? ? vcc vcco mosi miso sck cs en slow mstr pol pha ibias icmp gnd ip im miso mosi clk cs v dd mpu ltc6820 ? ? figure?19. multi-drop configuration using ltc6811-2 lt c6811-1/lt c6811-2 68111fb 45 for more information www.linear.com/LTC6811-1 operation ? ? ? ? 68111 f20 vdds en miso mosi sck cs vdd pol pha mstr icmp ibias gnd slow ip im miso mosi clk cs v dd mpu ltc6820 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo(nc) sdi(nc) sck(ipa) csb(ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 terminated unused port 100 ? ? ? ? 68111 f21 vdds en miso mosi sck cs vdd pol pha mstr icmp ibias gnd slow ip im miso mosi clk cs v dd mpu ltc6820 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo(ibias) sdi(icmp) sck(ipa) csb(ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 ltc6811-2 address = 00 figure?20. single device LTC6811-1 using 2-wire port a figure?21. single device ltc6811-2 using 2-wire port a lt c6811-1/lt c6811-2 68111fb 46 for more information www.linear.com/LTC6811-1 operation required bias 68111 f22 miso mosi clk cs v dd mpu v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo(nc) sdi(nc) sck(ipa) csb(ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 terminated unused port 100 20k 5k 68111 f23 miso mosi clk cs v dd mpu v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 a3 a2 a1 a0 sdo(ibias) sdi(icmp) sck(ipa) csb(ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 5k address = 00 figure?22. single device LTC6811-1 using 4-wire port a figure?23. single device ltc6811-2 using 4-wire port a isospi pulse detail two ltc6811 devices can communicate by transmitting and receiving differential pulses back and forth through an isolation barrier. the transmitter can output three voltage levels: +v a , 0v and -v a . a positive output results from ip sourcing current and im sinking current across load resistor r m . a negative voltage is developed by ip sinking and im sourcing. when both outputs are off, the load resistance forces the differential output to 0v. to eliminate the dc signal component and enhance reli - ability, the isospi uses two different pulse lengths. this allows four types of pulses to be transmitted, as shown in t able? 25. a +1 pulse will be transmitted as a positive pulse followed by a negative pulse. a C 1 pulse will be transmit - ted as a negative pulse followed by a positive pulse. the duration of each pulse is defined as t ?pw , since each is half of the required symmetric pair (the total isospi pulse duration is 2t ?pw ). table?25. isospi pulse types pulse type first level (t ?pw ) second level (t ?pw ) ending level long +1 +v a (150ns) Cv a (150ns) 0v long C1 Cv a (150ns) +v a (150ns) 0v short +1 +v a (50ns) Cv a (50ns) 0v short C1 Cv a (50ns) +v a (50ns) 0v a host microcontroller does not have to generate isospi pulses to use this 2- wire interface. the first ltc6811 in the system can communicate to the microcontroller using the 4- wire spi interface on its port a, then daisy-chain to other ltc6811 s using the 2- wire isospi interface on its port b. alternatively, the ltc6820 can be used to translate the spi signals into isospi pulses. lt c6811-1/lt c6811-2 68111fb 47 for more information www.linear.com/LTC6811-1 operation LTC6811-1 operation with port a configured for spi when the LTC6811-1 is operating with port a as a spi (isomd?= ?v C ), the spi detects one of four communication events: csb falling, csb rising, sck rising with sdi? =?0 and sck rising with sdi? = ?1. each event is converted into one of the four pulse types for transmission through the daisy chain. long pulses are used to transmit csb changes and short pulses are used to transmit data, as explained in table?26. table?26. port b (master) isospi port function communication event (port a spi) transmit ted pulse (port b isospi) csb rising long +1 csb falling long C1 sck rising edge, sdi?=?1 short +1 sck rising edge, sdi?=?0 short C1 on the other side of the isolation barrier (i.e. at the other end of the cable), the 2 nd ltc6811 will have isomd? = ?v reg . its port a operates as a slave isospi interface. it receives each transmitted pulse and reconstructs the spi signals internally, as shown in table?27. in addition, during a read command this port may transmit return data pulses. table?27. port a (slave) isospi port function received pulse (port a isospi) internal spi port action return pulse long +1 drive csb high none long C1 drive csb low short +1 1. set sdi?=?1 2. pulse sck short C1 pulse if reading a 0 bit (no return pulse if not in read mode or if reading a 1 bit) short C1 1. set sdi?=?0 2. pulse sck the lower isospi port (port a) never transmits long (csb) pulses. furthermore, a slave isospi port will only transmit short C1 pulses, never a +1 pulse. the master port recognizes a null response as a logic 1. this allows for multiple slave devices on a single cable without risk of collisions (multi-drop). +v tcmp ?v tcmp v ip ? v im +1 pulse t inv t 1/2pw +v tcmp ?v tcmp v ip ? v im t 1/2pw t inv t 1/2pw 68111 f24 ?1 pulse t 1/2pw t filt margin t filt margin t filt margin t filt margin t wndw t wndw margin margin figure?24. isospi pulse detail lt c6811-1/lt c6811-2 68111fb 48 for more information www.linear.com/LTC6811-1 operation figure?25 shows the isospi timing diagram for a read command to daisy-chained LTC6811-1 parts. the isomd pin is tied to v C on the bottom part so its port a is config - ured as a spi port (csb, sck, sdi and sdo). the isospi signals of three stacked devices are shown labeled with the port (a or b) and part number . note that iso b1 and iso a2 is actually the same signal, but shown on each end of the transmission cable that connects parts 1 and 2. likewise, iso b2 and iso a3 is the same signal, but with the cable delay shown between parts 2 and 3. bits w n -w 0 refer to the 16-bit command code and the 16-bit pec of a read command. at the end of bit w 0 , the three parts decode the read command and begin shifting out data, which is valid on the next rising edge of clock sck. bits x n -x 0 refer to the data shifted out by part 1. bits y n -y 0 refer to the data shifted out by part 2 and bits z n -z 0 refer to the data shifted out by part 3. all this data is read back from the sdo port on part 1 in a daisy-chained fashion. waking up the serial interface the serial ports (spi or isospi) will enter the low power idle state if there is no activity on port a for a time of t idle . the wakeup circuit monitors activity on pins 41 and 42. if isomd? =?v C , port a is in spi mode. activity on the csb or sck pin will wake up the spi interface. if isomd? =?v reg , port a is in isospi mode. differential activity on ipa-ima wakes up the isospi interface. the ltc6811 will be ready to communicate when the isospi state changes to ready within t wake or t ready , depending on the core state (see figure?1 and state descriptions for details). 68111 f25 sdi sck sdo csb iso a2 iso b2 iso a3 iso b1 read data command 6000 5000 4000 3000 2000 1000 0 t 7 t 6 t 5 t rtn t 11 t 10 t 2 t 1 t clk t 4 t 3 t rise t dsy(cs) t 8 t 9 t dsy(cs) z n-1 z n-1 z n z n w 0 w 0 w n w n y n-1 y n-1 y n y n w 0 w 0 x n-1 x n z 0 w n w n t dsy(d) t 10 figure?25. isospi timing diagram lt c6811-1/lt c6811-2 68111fb 49 for more information www.linear.com/LTC6811-1 operation figure? 26 illustrates the timing and the functionally equivalent circuit. common mode signals will not wake up the serial interface. the interface is designed to wake up after receiving a large signal single-ended pulse, or a low-amplitude symmetric pulse. the differential signal | sck(ipa) C csb(ima)|, must be at least v wake ?=?200mv for a minimum duration of t dwell ?=?240ns to qualify as a wake-up signal that powers up the serial interface. waking a daisy chainmethod 1 the ltc6811 -1 sends a long +1 pulse on port b after it is ready to communicate. in a daisy-chained configuration, this pulse wakes up the next device in the stack which will, in turn, wake up the next device. if there are n devices in the stack, all the devices are powered up within the time n ? t wake or n ? t ready , depending on the core state. for large stacks, the time n ? t wake may be equal to or larger than t idle . in this case, after waiting longer than the time of n ? t wake , the host may send another dummy byte and wait for the time n ? t ready , in order to ensure that all devices are in the ready state. method 1 can be used when all devices on the daisy chain are in the idle state. this guarantees that they propagate the wake-up signal up the daisy chain. however, this method will fail to wake up all devices when a device in the middle of the chain is in the ready state instead of idle. when this happens, the device in ready state will not propagate the wake-up pulse, so the devices above it will remain idle. this situation can occur when attempt - ing to wake up the daisy chain after only t idle of idle time (some devices may be idle, some may not). waking a daisy chainmethod 2 a more robust wake-up method does not rely on the built- in wake-up pulse, but manually sends isospi traffic for enough time to wake the entire daisy chain. at minimum, a pair of long isospi pulses (C1 and +1) is needed for each device, separated by more than t ready or t wake (if the core state is standby or sleep, respectively), but less than t idle . this allows each device to wake up and propagate the next pulse to the following device. this method works even if some devices in the chain are not in the idle state. in practice, implementing method 2 requires toggling the csb pin (of the ltc6820, or bottom LTC6811-1 with isomd? = ?0) to generate the long isospi pulses. alternatively, dummy commands (such as rdcfga) can be executed to generate the long isospi pulses. data link layer all data transfers on ltc6811 occur in byte groups. every byte consists of 8 bits. bytes are transferred with the most significant bit (msb) first. csb must remain low for the entire duration of a command sequence, including be - tween a command byte and subsequent data. on a write command, data is latched in on the rising edge of csb. 68111 f26 csb or ima sck or ipa |sck(ipa) - csb(ima)| wake-up state rejects common mode noise wake-up csb or ima sck or ipa low power mode t idle > 4.5ms t ready < 10s t dwell = 240ns v wake = 200mv low power mode ok to communicate t dwell = 240ns delay retriggerable t idle = 5.5ms one-shot figure?26. wake-up detection and idle timer lt c6811-1/lt c6811-2 68111fb 50 for more information www.linear.com/LTC6811-1 operation network layer packet error code the packet error code (pec) is a 15-bit cyclic redundancy check (crc) value calculated for all of the bits in a register group in the order they are passed, using the initial pec value of 000000000010000 and the following character - istic polynomial: x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1. to calculate the 15-bit pec value, a simple procedure can be established: 1. initialize the pec to 000000000010000 (pec is a 15-bit register group). 2. for each bit din coming into the pec register group, set in0?=?din xor pec [14] in3?=?in0 xor pec [2] in4?=?in0 xor pec [3] in7?=?in0 xor pec [6] in8?=?in0 xor pec [7] in10?=?in0 xor pec [9] in14?=?in0 xor pec [13]. 3. up date the 15-bit pec as follows pec [14]?=?in14, pec [13]?=?pec [12], pec [12]?=?pec [11], pec [11]?=?pec [10], pec [10]?=?in10, pec [9]?=?pec [8], pec [8]?=?in8, pec [7]?=?in7, pec [6]?=?pec [5], pec [5]?=?pec [4], pec [4]?=?in4, pec [3]?=?in3, pec [2]?=?pec [1], pec [1]?=?pec [0], pec [0]?=?in0. 4. go back to step 2 until all the data is shifted. the final pec (16 bits) is the 15- bit value in the pec register with a 0 bit appended to its lsb. figure?27 illustrates the algorithm described above. an example to calculate the pec for a 16-bit word (0x0001) is listed in table?28. the pec for 0x0001 is computed as 0x3d6e after stuffing a 0 bit at the lsb. for longer data streams, the pec is valid at the end of the last bit of data sent to the pec register. 68111 f27 din i/p o/p i/p pec register bit x xor gate x 0 1 2 3 4 5 6 7 8 9 14 10 11 12 13 figure?27. 15-bit pec computation circuit lt c6811-1/lt c6811-2 68111fb 51 for more information www.linear.com/LTC6811-1 operation table?28. pec calculation for 0x0001 pec[14] 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 pec[13] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 pec[12] 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 pec[11] 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 pec[10] 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 1 pec[9] 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 pec[8] 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 pec[7] 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 pec[6] 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 pec[5] 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 pec[4] 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 pec[3] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 pec[2] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 pec[1] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 pec[0] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 in14 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 in10 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 pec word in8 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 in7 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 i n4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 in3 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 in0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 din 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 clock cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 lt c6811-1/lt c6811-2 68111fb 52 for more information www.linear.com/LTC6811-1 operation ltc6811 calculates pec for any command or data received and compares it with the pec following the command or data. the command or data is regarded as valid only if the pec matches. ltc6811 also attaches the calculated pec at the end of the data it shifts out. table?29 shows the format of pec while writing to or reading from ltc6811. while writing any command to ltc6811, the command bytes cmd0 and cmd1 (see table?36 and table?37) and the pec bytes pec0 and pec1 are sent on port a in the following order: c md0, cmd1, pec0, pec1 after a broadcast write command to daisy-chained LTC6811-1 devices, data is sent to each device followed by the pec. for example, when writing the configuration register group to two daisy-chained devices (primary device p, stacked device s), the data will be sent to the primary device on port a in the following order: cfg r0(s), , cfgr5(s), pec0(s), pec1(s), cfg r0(p), , cfgr5(p), pec0(p), pec1(p) after a read command for daisy-chained devices, each device shifts out its data and the pec that it computed for its data on port a followed by the data received on port b. for example, when reading status register group b from two daisy-chained devices (primary device p, stacked device s), the primary device sends out data on port a in the following order: stb r0(p), , stbr5(p), pec0(p), pec1(p), stb r0(s), , stbr5(s), pec0(s), pec1(s) address commands (ltc6811-2 only) an address command is one in which only the addressed device on the bus responds. address commands are used only with ltc6811 -2 parts. all commands are compatible with addressing. see bus protocols for address command format. broadcast commands (LTC6811-1 or ltc6811-2) a broadcast command is one to which all devices on the bus will respond, regardless of device address. this com - mand format can be used with LTC6811-1 and ltc6811-2 parts. see bus protocols for broadcast command format. with broadcast commands all devices can be sent com - mands simultaneously. in parallel (ltc6811 -2) configurations, broadcast com - mands are useful for initiating adc conversions or for sending write commands when all parts are being written with the same data. the polling function (automatic at the end of adc commands, or manual using the pladc com - mand) can also be used with broadcast commands, but not with parallel isospi devices. likewise, broadcast read commands should not be used in the parallel configuration (either spi or isospi). daisy-chained ( LTC6811-1) configurations support broad - cast commands only, because they have no addressing. all devices in the chain receive the command bytes simul - taneously. for example, to initiate adc conversions in a stack of devices, a single adcv command is sent, and all devices will start conversions at the same time. for read and write commands, a single command is sent, and then the stacked devices effectively turn into a cascaded shift register, in which data is shifted through each device to the next higher (on a write) or the next lower (on a read) device in the stack. see the serial interface section. polling methods the simplest method to determine adc completion is for the controller to start an adc conversion and wait for the specified conversion time to pass before reading the results. both LTC6811-1 and ltc6811 -2 also allow polling to determine adc completion. in parallel configurations that communicate in spi mode (isomd pin tied low), there are two methods of polling. table?29. write/read pec format name rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pec0 rd/wr pec[14] pec[13] pec[12] pec[11] pec[10] pec[9] pec[8] pec[7] pec1 rd/wr pec[6] pec[5] pec[4] pec[3] pec[2] pec[1] pec[0] 0 lt c6811-1/lt c6811-2 68111fb 53 for more information www.linear.com/LTC6811-1 operation the first method is to hold csb low after an adc con - version command is sent. after entering a conversion command, the sdo line is driven low when the device is busy per forming conversions. sdo is pulled high when the device completes conversions. however , sdo will also go back high when csb goes high even if the device has not completed the conversion (figure?28). an addressed device drives the sdo line based on its status alone. a problem with this method is that the controller is not free to do other serial communication while waiting for adc conversions to complete. the next method overcomes this limitation. the controller can send an adc start command, perform other tasks, and then send a poll adc converter status (pladc) command to determine the status of the adc conversions (figure?29). after entering the pladc command, sdo will go low if the device is busy performing conversions. sdo is pulled high at the end of conversions. however, sdo will also go high when csb goes high even if the device has not completed the conversion. in parallel configurations that communicate in isospi mode, the low side port transmits a data pulse only in response to a master isospi pulse received by it. so, after entering the command in either method of polling described above, isospi data pulses are sent to the part to update the con - version status. these pulses can be sent using ltc6820 by simply clocking its sck pin. in response to this pulse, the lt c6811 -2 sends back a low isospi pulse if it is still busy performing conversions or a high data pulse if it has completed the conversions. if a csb high isospi pulse is sent to the device, it exits the polling command. 68111 f28 sdi sck t cycle sdo csb msb(cmd) lsb(pec) bit 14(cmd) figure?28. sdo polling after an adc conversion command (parallel configuration) 68111 f29 sdi sck sdo csb msb(cmd) lsb(pec) conversion done bit 14(cmd) figure?29. sdo polling using pladc command (parallel configuration) lt c6811-1/lt c6811-2 68111fb 54 for more information www.linear.com/LTC6811-1 operation in a daisy-chained configuration of n stacked devices, the same two polling methods can be used. if the bottom device communicates in spi mode, the sdo of the bottom device indicates the conversion status of the entire stack i.e. sdo will remain low until all the devices in the stack have completed the conversions. in the first method of polling, after an adc conversion command is sent, clock pulses are sent on sck while keeping csb low. the sdo status becomes valid only at the end of n clock pulses on sck. during the first n clock pulses, the bottom LTC6811-1 in the daisy chain will output 0 or a low data pulse. after n clock pulses, the output data from the bottom LTC6811-1 gets updated for every clock pulse that follows (figure?30). in the second method, the pladc command is sent fol - lowed by clock pulses on sck while keeping csb low. similar to the first method, the sdo status is valid only after n clock cycles on sck and gets updated after every clock cycle that follows (figure?31). if the bottom device communicates in isospi mode, isospi data pulses are sent to the device to update the conversion status. using ltc6820, this can be achieved by just clock - ing its sck pin. the conversion status is valid only after the bottom ltc6811 device receives n isospi data pulses and the status gets updated for every isospi data pulse that follows. the device returns a low data pulse if any of the devices in the stack is busy performing conversions and returns a high data pulse if all the devices are free. 68111 f30 sdi sck t cycle (all devices) sdo csb msb(cmd) lsb(pec) 1 2 n figure?30. sdo polling after an adc conversion command (daisy-chain configuration) 68111 f31 sdi sck sdo csb msb(cmd) lsb(pec) 1 2 n conversion done figure?31. sdo polling using pladc command (daisy-chain configuration) lt c6811-1/lt c6811-2 68111fb 55 for more information www.linear.com/LTC6811-1 operation command format: the formats for the broadcast and address commands are shown in table?36 and table?37 respectively. the 11-bit command code cc[ 10 :0] is the same for a broadcast or an address command. a list of all the command codes is shown in table?38. a broadcast command has a value 0 for cmd0 [7] through cmd0 [3]. an address command has a value 1 for cmd0 [7] fol - lowed by the 4- bit address of the device ( a3, a2, a1, a0 ) in bits cmd0 [6:3] . an addressed device will respond to an address command only if the physical address of the device on pins a3 to a0 match the address specified in the address command. the pec for broadcast and ad - dress commands must be computed on the entire 16-bit command (c md0 and cmd1 ). bus protocols protocol format: the protocol formats for both broadcast and address commands are depicted in table?31 through table?35. table?30 is the key for reading the protocol diagrams. table?30. protocol key cmd0 command byte 0 (see table?36 and table?37) cmd1 command byte 1 (see table?36 and table?37) pec0 packet error code byte 0 (see table?29) pec1 packet error code byte 1 (see table?29) n number of bytes continuation of protocol master to slave slave to master table?31. broadcast/address poll command 8 8 8 8 cmd0 cmd1 pec0 pec1 poll data table?32. broadcast write command 8 8 8 8 8 8 8 8 8 8 cmd0 cmd1 pec0 pec1 data byte low data byte high pec0 pec1 shift byte 1 shift byte n table?33. address write command 8 8 8 8 8 8 8 8 cmd0 cmd1 pec0 pec1 data byte low data byte high pec0 pec1 table?34. broadcast read command 8 8 8 8 8 8 8 8 8 8 cmd0 cmd1 pec0 pec1 data byte low data byte high pec0 pec1 shift byte 1 shift byte n table?35. address read command 8 8 8 8 8 8 8 8 cmd0 cmd1 pec0 pec1 data byte low data byte high pec0 pec1 table?36. broadcast command format name rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmd0 wr 0 0 0 0 0 cc[10] cc[9] cc[8] cmd1 wr cc[7] cc[6] cc[5] cc[4] cc[3] cc[2] cc[1] cc[0] table?37. address command format name rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmd0 wr 1 a3* a2* a1* a0* cc[10] cc[9] cc[8] cmd1 wr cc[7] cc[6] cc[5] cc[4] cc[3] cc[2] cc[1] cc[0] *ax is address bit x lt c6811-1/lt c6811-2 68111fb 56 for more information www.linear.com/LTC6811-1 operation commands table? 38 lists all the commands and their options for both ltc6811 -1 and ltc6811-2. the command set is backwards compatible with ltc6804. table?38. command codes command description name cc[10:0] - command code 10 9 8 7 6 5 4 3 2 1 0 write configuration register group a wrcfga 0 0 0 0 0 0 0 0 0 0 1 write configuration register group b* wrcfgb* 0 0 0 0 0 1 0 0 1 0 0 read configuration register group a rdcfga 0 0 0 0 0 0 0 0 0 1 0 read configuration register group b* rdcfgb* 0 0 0 0 0 1 0 0 1 1 0 read cell v oltage register group a rdcva 0 0 0 0 0 0 0 0 1 0 0 read cell voltage register group b rdcvb 0 0 0 0 0 0 0 0 1 1 0 read cell voltage register group c rdcvc 0 0 0 0 0 0 0 1 0 0 0 read cell voltage register group d rdcvd 0 0 0 0 0 0 0 1 0 1 0 read cell voltage register group e* rdcve* 0 0 0 0 0 0 0 1 0 0 1 read cell voltage register group f* rdcvf* 0 0 0 0 0 0 0 1 0 1 1 read auxiliary register group a rdauxa 0 0 0 0 0 0 0 1 1 0 0 read auxiliary register group b rdauxb 0 0 0 0 0 0 0 1 1 1 0 read auxiliary register group c* rdauxc* 0 0 0 0 0 0 0 1 1 0 1 read auxiliary register group d* rdauxd* 0 0 0 0 0 0 0 1 1 1 1 read status register group a rdstata 0 0 0 0 0 0 1 0 0 0 0 read status register group b rdstatb 0 0 0 0 0 0 1 0 0 1 0 write s control register group wrsctrl 0 0 0 0 0 0 1 0 1 0 0 write pwm register group wrpwm 0 0 0 0 0 1 0 0 0 0 0 write pwm/s control register group b* wrpsb* 0 0 0 0 0 0 1 1 1 0 0 read s control register group rdsctrl 0 0 0 0 0 0 1 0 1 1 0 read pwm register group rdpwm 0 0 0 0 0 1 0 0 0 1 0 lt c6811-1/lt c6811-2 68111fb 57 for more information www.linear.com/LTC6811-1 operation command description name cc[10:0] - command code 10 9 8 7 6 5 4 3 2 1 0 read pwm/s control register group b* rdpsb* 0 0 0 0 0 0 1 1 1 1 0 start s control pulsing and poll status stsctrl 0 0 0 0 0 0 1 1 0 0 1 clear s control register group clrsctrl 0 0 0 0 0 0 1 1 0 0 0 start cell voltage adc conversion and poll status adcv 0 1 md[1] md[0] 1 1 dcp 0 ch[2] ch[1] ch[0] start open wire adc conversion and poll status adow 0 1 md[1] md[0] pup 1 dcp 1 ch[2] ch[1] ch[0] start self test cell voltage conversion and poll status cvst 0 1 md[1] md[0] st[1] st[0] 0 0 1 1 1 start overlap measurement of cell 7 voltage adol 0 1 md[1] md[0] 0 0 dcp 0 0 0 1 start gpios adc conversion and poll status adax 1 0 md[1] md[0] 1 1 0 0 chg [2] chg [1] chg [0] start gpios adc conversion with digital redundancy and poll status adaxd 1 0 md[1] md[0] 0 0 0 0 chg [2] chg [1] chg [0] start self test gpios conversion and poll status axst 1 0 md[1] md[0] st[1] st[0] 0 0 1 1 1 start status group adc conversion and poll status adstat 1 0 md[1] md[0] 1 1 0 1 chst [2] chst [1] chst [0] start status group adc conversion with digital redundancy and poll status adstatd 1 0 md[1] md[0] 0 0 0 1 chst [2] chst [1] chst [0] start self test status group conversion and poll status statst 1 0 md[1] md[0] st[1] st[0] 0 1 1 1 1 start combined cell voltage and gpio1, gpio2 conversion and poll status adcvax 1 0 md[1] md[0] 1 1 dcp 1 1 1 1 start combined cell voltage and sc conversion and poll status adcvsc 1 0 md[1] md[0] 1 1 dcp 0 1 1 1 clear cell voltage register groups clrcell 1 1 1 0 0 0 1 0 0 0 1 clear auxiliar y register groups clraux 1 1 1 0 0 0 1 0 0 1 0 clear status register groups clrstat 1 1 1 0 0 0 1 0 0 1 1 poll adc conversion status pladc 1 1 1 0 0 0 1 0 1 0 0 diagnose mux and poll status diagn 1 1 1 0 0 0 1 0 1 0 1 write comm register group wrcomm 1 1 1 0 0 1 0 0 0 0 1 read comm register group rdcomm 1 1 1 0 0 1 0 0 0 1 0 start i 2 c /spi communication stcomm 1 1 1 0 0 1 0 0 0 1 1 *these commands provided for for ward-compatibility with ltc6813/6812. lt c6811-1/lt c6811-2 68111fb 58 for more information www.linear.com/LTC6811-1 operation table?39. command bit descriptions name description values md[1:0] adc mode md adcopt(cfgr0[0])?=?0 adcopt(cfgr0[0]) = 1 00 422hz mode 1khz mode 01 27khz mode (fast) 14khz mode 10 7khz mode (normal) 3khz mode 11 26hz mode (filtered) 2khz mode dcp discharge permitted dcp 0 discharge not permitted 1 discharge permitted ch[2:0] cell selection for adc conversion total conversion time in the 8 adc modes ch 27khz 14khz 7khz 3khz 2khz 1khz 422hz 26hz 000 all cells 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 7.2ms 12.8ms 201ms 001 cell 1 and cell 7 201s 230s 405s 501s 754s 1.2ms 2.2ms 34ms 010 cell 2 and cell 8 011 cell 3 and cell 9 100 cell 4 and cell 10 101 cell 5 and cell 11 110 cell 6 and cell 12 pup pull-up/pull-down current for open wire conversions pup 0 pull-down current 1 pull-up current st[1:0] self test mode selection self test conversion result st 27khz 14khz 7khz 3khz 2khz 1khz 422hz 26hz 01 self test 1 0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 0x9555 0x9555 10 self test 2 0x6a9a 0x6aac 0x6aaa 0x6aaa 0x6aaa 0x6aaa 0x6aaa 0x6aaa chg[2:0] gpio selection for adc conversion total conversion time in the 8 adc modes chg 27khz 14khz 7khz 3khz 2khz 1khz 422hz 26hz 000 gpio 1-5, 2 nd ref 1.1ms 1.3ms 2.3ms 3.0ms 4.4ms 7.2ms 12.8ms 201ms 001 gpio 1 201s 230s 405s 501s 754s 1.2ms 2.2ms 34ms 010 gpio 2 011 gpio 3 100 gpio 4 101 gpio 5 110 2 nd reference chst[2:0]* status group selection total conversion time in the 8 adc modes chst 27khz 14khz 7khz 3khz 2khz 1khz 422hz 26hz 000 sc, itmp, va, vd 748s 865s 1.6ms 2.0ms 3.0ms 4.8ms 8.5ms 134ms 001 sc 201s 230s 405s 501s 754s 1.2ms 2.2ms 34ms 010 itmp 011 va 100 vd *note: valid options for chst in adstat command are 0-4. if chst is set to 5/6 in adstat command, the ltc6811 treats it like adax command with chg ?=?5/6. lt c6811-1/lt c6811-2 68111fb 59 for more information www.linear.com/LTC6811-1 operation memory map table?40. configuration register group register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cfgr0 rd/wr gpio5 gpio4 gpio3 gpio2 gpio1 refon dten adcopt cfgr1 rd/wr vuv[7] vuv[6] vuv[5] vuv[4] vuv[3] vuv[2] vuv[1] vuv[0] cfgr2 rd/wr vov[3] vov[2] vov[1] vov[0] vuv[11] vuv[10] vuv[9] vuv[8] cfgr3 rd/wr vov[11] vov[10] vov[9] vov[8] vov[7] vov[6] vov[5] vov[4] cfgr4 rd/wr dcc8 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 cfgr5 rd/wr dcto[3] dcto[2] dcto[1] dcto[0] dcc12 dcc11 dcc10 dcc9 table?41. cell voltage register group a register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvar0 rd c1v[7] c1v[6] c1v[5] c1v[4] c1v[3] c1v[2] c1v[1] c1v[0] cvar1 rd c1v[15] c1v[14] c1v[13] c1v[12] c1v[11] c1v[10] c1v[9] c1v[8] cvar2 rd c2v[7] c2v[6] c2v[5] c2v[4] c2v[3] c2v[2] c2v[1] c2v[0] cvar3 rd c2v[15] c2v[14] c2v[13] c2v[12] c2v[11] c2v[10] c2v[9] c2v[8] cvar4 rd c3v[7] c3v[6] c3v[5] c3v[4] c3v[3] c3v[2] c3v[1] c3v[0] cvar5 rd c3v[15] c3v[14] c3v[13] c3v[12] c3v[11] c3v[10] c3v[9] c3v[8] table?42. cell voltage register group b register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvbr0 rd c4v[7] c4v[6] c4v[5] c4v[4] c4v[3] c4v[2] c4v[1] c4v[0] cvbr1 rd c4v[15] c4v[14] c4v[13] c4v[12] c4v[11] c4v[10] c4v[9] c4v[8] cvbr2 rd c5v[7] c5v[6] c5v[5] c5v[4] c5v[3] c5v[2] c5v[1] c5v[0] cvbr3 rd c5v[15] c5v[14] c5v[13] c5v[12] c5v[11] c5v[10] c5v[9] c5v[8] cvbr4 rd c6v[7] c6v[6] c6v[5] c6v[4] c6v[3] c6v[2] c6v[1] c6v[0] cvbr5 rd c6v[15] c6v[14] c6v[13] c6v[12] c6v[11] c6v[10] c6v[9] c6v[8] table?43. cell voltage register group c register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvcr0 rd c7v[7] c7v[6] c7v[5] c7v[4] c7v[3] c7v[2] c7v[1] c7v[0] cvcr1 rd c7v[15] c7v[14] c7v[13] c7v[12] c7v[11] c7v[10] c7v[9] c7v[8] cvcr2* rd c8v[7]* c8v[6]* c8v[5]* c8v[4]* c8v[3]* c8v[2]* c8v[1]* c8v[0]* cvcr3* rd c8v[15]* c8v[14]* c8v[13]* c8v[12]* c8v[11]* c8v[10]* c8v[9]* c8v[8]* cvcr4 rd c9v[7] c9v[6] c9v[5] c9v[4] c9v[3] c9v[2] c9v[1] c9v[0] cvcr5 rd c9v[15] c9v[14] c9v[13] c9v[12] c9v[11] c9v[10] c9v[9] c9v[8] *after performing the adol command, cvcr2 and cvcr3 of cell voltage register group c will contain the result of measuring cell 7 from adc1. lt c6811-1/lt c6811-2 68111fb 60 for more information www.linear.com/LTC6811-1 operation table?44. cell voltage register group d register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cvdr0 rd c10v[7] c10v[6] c10v[5] c10v[4] c10v[3] c10v[2] c10v[1] c10v[0] cvdr1 rd c10v[15] c10v[14] c10v[13] c10v[12] c10v[11] c10v[10] c10v[9] c10v[8] cvdr2 rd c11v[7] c11v[6] c11v[5] c11v[4] c11v[3] c11v[2] c11v[1] c11v[0] cvdr3 rd c11v[15] c11v[14] c11v[13] c11v[12] c11v[11] c11v[10] c11v[9] c11v[8] cvdr4 rd c12v[7] c12v[6] c12v[5] c12v[4] c12v[3] c12v[2] c12v[1] c12v[0] cvdr5 rd c12v[15] c12v[14] c12v[13] c12v[12] c12v[11] c12v[10] c12v[9] c12v[8] table?45. auxiliary register group a register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 avar0 rd g1v[7] g1v[6] g1v[5] g1v[4] g1v[3] g1v[2] g1v[1] g1v[0] avar1 rd g1v[15] g1v[14] g1v[13] g1v[12] g1v[11] g1v[10] g1v[9] g1v[8] avar2 rd g2v[7] g2v[6] g2v[5] g2v[4] g2v[3] g2v[2] g2v[1] g2v[0] avar3 rd g2v[15] g2v[14] g2v[13] g2v[12] g2v[11] g2v[10] g2v[9] g2v[8] avar4 rd g3v[7] g3v[6] g3v[5] g3v[4] g3v[3] g3v[2] g3v[1] g3v[0] avar5 rd g3v[15] g3v[14] g3v[13] g3v[12] g3v[11] g3v[10] g3v[9] g3v[8] table?46. auxiliary register group b register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 avbr0 rd g4v[7] g4v[6] g4v[5] g4v[4] g4v[3] g4v[2] g4v[1] g4v[0] avbr1 rd g4v[15] g4v[14] g4v[13] g4v[12] g4v[11] g4v[10] g4v[9] g4v[8] avbr2 rd g5v[7] g5v[6] g5v[5] g5v[4] g5v[3] g5v[2] g5v[1] g5v[0] avbr3 rd g5v[15] g5v[14] g5v[13] g5v[12] g5v[11] g5v[10] g5v[9] g5v[8] avbr4 rd ref[7] ref[6] ref[5] ref[4] ref[3] ref[2] ref[1] ref[0] avbr5 rd ref[15] ref[14] ref[13] ref[12] ref[11] ref[10] ref[9] ref[8] table?47. status register group a register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 star0 rd sc[7] sc[6] sc[5] sc[4] sc[3] sc[2] sc[1] sc[0] star1 rd sc[15] sc[14] sc[13] sc[12] sc[11] sc[10] sc[9] sc[8] star2 rd itmp[7] itmp[6] itmp[5] itmp[4] itmp[3] itmp[2] itmp[1] itmp[0] star3 rd itmp[15] itmp[14] itmp[13] itmp[12] itmp[11] itmp[10] itmp[9] itmp[8] star4 rd va[7] va[6] va[5] va[4] va[3] va[2] va[1] va[0] star5 rd va[15] va[14] va[13] va[12] va[11] va[10] va[9] va[8] lt c6811-1/lt c6811-2 68111fb 61 for more information www.linear.com/LTC6811-1 operation table?48. status register group b register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stbr0 rd vd[7] vd[6] vd[5] vd[4] vd[3] vd[2] vd[1] vd[0] stbr1 rd vd[15] vd[14] vd[13] vd[12] vd[11] vd[10] vd[9] vd[8] stbr2 rd c4ov c4uv c3ov c3uv c2ov c2uv c1ov c1uv stbr3 rd c8ov c8uv c7ov c7uv c6ov c6uv c5ov c5uv stbr4 rd c12ov c12uv c11ov c11uv c10ov c10uv c9ov c9uv stbr5 rd rev[3] rev[2] rev[1] rev[0] rsvd rsvd muxfail thsd table?49. comm register group register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comm0 rd/wr icom0[3] icom0[2] icom0[1] icom0[0] d0[7] d0[6] d0[5] d0[4] comm1 rd/wr d0[3] d0[2] d0[1] d0[0] fcom0[3] fcom0[2] fcom0[1] fcom0[0] comm2 rd/wr icom1[3] icom1[2] icom1[1] icom1[0] d1[7] d1[6] d1[5] d1[4] comm3 rd/wr d1[3] d1[2] d1[1] d1[0] fcom1[3] fcom1[2] fcom1[1] fcom1[0] comm4 rd/wr icom2[3] icom2[2] icom2[1] icom2[0] d2[7] d2[6] d2[5] d2[4] comm5 rd/wr d2[3] d2[2] d2[1] d2[0] fcom2[3] fcom2[2] fcom2[1] fcom2[0] table?50. s control register group register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sctrl0 rd/wr sctl2[3] sctl2[2] sctl2 [1] sctl2[0] sctl1[3] sctl1[2] sctl1[1] sctl1[0] sctrl1 rd/wr sctl4[3] sctl4[2] sctl4[1] sctl4[0] sctl3[3] sctl3[2] sctl3[1] sctl3[0] sctrl2 rd/wr sctl6[3] sctl6[2] sctl6[1] sc6tl[0] sctl5[3] sctl5[2] sctl5[1] sctl5[0] sctrl3 rd/wr sctl8[3] sctl8[2] sctl8[1] sctl8[0] sctl7[3] sctl7[2] sctl7[1] sctl7[0] sctrl4 rd/wr sctl10[3] sctl10[2] sctl10[1] sctl10[0] sctl9[3] sctl9[2] sctl9[1] sctl9[0] sctrl5 rd/wr sctl12[3] sctl12[2] sctl12[1] sctl12[0] sctl11[3] sctl11[2] sctl11[1] sctl11[0] table?51. pwm register group register rd/wr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwmr0 rd/wr pwm2[3] pwm2[2] pwm2 [1] pwm2[0] pwm1[3] pwm1[2] pwm1[1] pwm1[0] pwmr1 rd/wr pwm4[3] pwm4[2] pwm4[1] pwm4[0] pwm3[3] pwm3[2] pwm3[1] pwm3[0] pwmr2 rd/wr pwm6[3] pwm6[2] pwm6[1] pwm6[0] pwm5[3] pwm5[2] pwm5[1] pwm5[0] pwmr3 rd/wr pwm8[3] pwm8[2] pwm8[1] pwm8[0] pwm7[3] pwm7[2] pwm7[1] pwm7[0] pwmr4 rd/wr pwm10[3] pwm10[2] pwm10[1] pwm10[0] pwm9[3] pwm9[2] pwm9[1] pwm9[0] pwmr5 rd/wr pwm12[3] pwm12[2] pwm12[1] pwm12[0] pwm11[3] pwm11[2] pwm11[1] pwm11[0] lt c6811-1/lt c6811-2 68111fb 62 for more information www.linear.com/LTC6811-1 operation table?52. memory bit descriptions name description values gpiox gpiox pin control write: 0 -> gpiox pin pull-down on; 1-> gpiox pin pull-down off (default) read: 0 -> gpiox pin at logic 0; 1 -> gpiox pin at logic 1 refon reference powered up 1 -> reference remains powered up until w atchdog timeout 0 -> reference shuts down after conversions (default) dten discharge timer enable (read onl y) 1 -> enables the discharge timer for discharge switches 0 -> disables discharge timer adcopt adc mode option bit adcopt: 0 -> selects modes 27khz, 7khz, 422hz or 26hz with md[1:0] bits in adc conversion commands (default) 1 -> selects modes 14khz, 3khz, 1khz or 2khz with md[1:0] bits in adc conversion commands vuv undervoltage comparison voltage* comparison voltage?=?(vuv + 1) ? 16 ? 100v default: vuv?=?0x000 vov overvoltage comparison v oltage* comparison voltage?=?vov ? 16 ? 100v default: vov?=?0x000 dcc [x] discharge cell x x? =?1 to 12 1 -> t urn on shorting switch for cell x 0 -> t urn off shorting switch for cell x (default) dcto discharge time out value dcto (write) 0 1 2 3 4 5 6 7 8 9 a b c d e f time (min) disabled 0.5 1 2 3 4 5 10 15 20 30 40 60 75 90 120 dcto (read) 0 1 2 3 4 5 6 7 8 9 a b c d e f time left (min) disabled or timeout 0 to 0.5 0.5 to 1 1 to 2 2 to 3 3 to 4 4 to 5 5 to 10 10 to 15 15 to 20 20 to 30 30 to 40 40 to 60 60 to 75 75 to 90 90 to 120 cxv cell x voltage* x?=?1 to 12 16-bit adc measurement v alue for cell x cell voltage for cell x?=?cxv ? 100v cxv is reset to 0xffff on power -up and after clear command gxv gpio x voltage* x?=?1 to 5 16-bit adc measurement v alue for gpiox voltage for gpiox?=?gxv ? 100v gxv is reset to 0xffff on power -up and after clear command ref 2 nd reference voltage* 16-bit adc measurement v alue for 2 nd reference voltage for 2 nd reference?=?ref ? 100v normal range is within 2.99v to 3.01v considering data sheet limits, hysteresis and long term drift sc sum of cells measurement* 16-bit adc measurement v alue of the sum of all cell voltages sum of all cells voltage?=?sc ? 100v ? 20 itmp internal die temperature* 16-bit adc measurement v alue of internal die temperature temperature measurement (c)?=?itmp ? 100v/7.5mv/c C 273c va analog power supply voltage* 16-bit adc measurement v alue of analog power supply voltage analog power supply voltage?=?v a ? 100v the value of va is set by external components and should be in the range 4.5v to 5.5v for normal operation vd digital power supply voltage* 16-bit adc measurement v alue of digital power supply voltage digital power supply voltage?=?vd ? 100v normal range is within 2.7v to 3.6v cxov cell x overvoltage flag x?=?1 to 12 cell voltage compared to vov comparison v oltage 0 -> cell x not flagged for over voltage condition; 1-> cell x flagged lt c6811-1/lt c6811-2 68111fb 63 for more information www.linear.com/LTC6811-1 operation name description values cxuv cell x undervoltage flag x?=?1 to 12 cell voltage compared to vuv comparison v oltage 0 -> cell x not flagged for under voltage condition; 1-> cell x flagged rev revision code device revision code rsvd reserved bits read: read back value is always 0 muxfail multiplexer self test result read: 0 -> multiplexer passed self test; 1 -> multiplexer failed self test thsd thermal shutdown status read: 0 -> thermal shutdown has not occurred; 1 -> thermal shutdown has occurred thsd bit cleared to 0 on read of status register group b sctlx [ x] s pin control bits 0000 C drive s pin high (de-asserted) 0001 C send 1 high pulse on s pin 0010 C send 2 high pulses on s pin 0011 C send 3 high pulses on s pin 0100 C send 4 high pulses on s pin 0101 C send 5 high pulses on s pin 0110 C send 6 high pulses on s pin 0111 C send 7 high pulses on s pin 1xxx C drive s pin low (asserted) pwmx [x] pwm discharge control 0000 C selects 0% discharge duty cycle if dccx?=?1 and watchdog timer has expired 0001 C selects 6.7% discharge duty cycle if dccx?=?1 and watchdog timer has expired 0010 C selects 13.3% discharge duty cycle if dccx?=?1 and watchdog timer has expired 1110 C selects 93.3% discharge duty cycle if dccx?=?1 and watchdog timer has expired 1111 C selects 100% discharge duty cycle if dccx?=?1 and watchdog timer has expired icomn initial communication control bits write i 2 c 0110 0001 0000 0111 start stop blank no transmit spi 1000 1010 1001 1111 csb low csb falling edge csb high no transmit read i 2 c 0110 0001 0000 0111 start from master stop from master sda low between bytes sda high between bytes spi 0111 dn i 2 c/spi communication data byte data transmitted (received) to (from) i 2 c/spi slave device fcomn final communication control bits write i 2 c 0000 1000 1001 master ack master nack master nack + stop spi x000 1001 csb low csb high read i 2 c 0000 0111 1111 0001 1001 ack from master ack from slave nack from slave ack from slave + stop from master nack from slave + stop from master spi 1111 *voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits. lt c6811-1/lt c6811-2 68111fb 64 for more information www.linear.com/LTC6811-1 applications information providing dc power simple linear regulator the primary supply pin for the ltc6811 is the 5v (0.5v) v reg input pin. to generate the required 5v supply for v reg , the drive pin can be used to form a discrete regulator with the addition of a few external components, as shown in figure?32. the drive pin provides a 5.7v output, capable of sourcing 1ma . when buffered with an npn transistor, this provides a stable 5v over temperature. the npn transistor should be chosen to have a sufficient beta over temperature (> 40) to supply the necessary supply current. the peak v reg current requirement of the ltc6811 approaches 30ma when simultaneously communicating over isospi and making adc conversions. if the v reg pin is required to support any additional load, a transistor with an even higher beta may be required. the npn collector can be powered from any voltage source that is a minimum 6v above v C . this includes the cells that are being monitored, or an unregulated power supply. a 100/100nf rc decoupling network is recommended for the collector power connection to protect the npn from transients. the emitter of the npn should be bypassed with a 1f capacitor. larger capacitance should be avoided since this will increase the wake-up time of the ltc6811. some attention should be given to the thermal characteristic of the npn, as there can be significant heating with a high collector voltage. 1f 0.1f 100 68111 f32 wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 1f 1f ltc6811 nsv1c201mz4 figure?32. simple v reg power source using npn pass transistor improved regulator power efficiency for improved efficiency when powering the ltc6811 from the cell stack, v reg may be powered from a dc/dc converter, rather than the npn pass transistor. an ideal circuit is based on linear technology s lt3990 step- down regulator, as shown in figure?33. a 470 resistor is recommended between the battery stack and the lt3990 input; this will prevent in-rush current when connecting to the stack and it will reduce conducted emi. the en/uvlo pin should be connected to the drive pin, which will put the lt3990 into a low power state when the ltc6811 is in the sleep state. v in boost lt3990 sw en/uvlo pg rt 0.22f 22pf 374k f = 400khz 22f 2.2f v in 28v to 62v v reg 5v 40ma 1m 316k 470 33h bd fb gnd off on 68111 f33 figure?33. v reg powered from cell stack with high efficiency regulator fully isolated power a dc/dc converter can provide isolated power for either the ltc6811 v + , v reg or both. the circuit in figure?34, along with the isospi transformer isolation, provides an example where the ltc6811 circuitry is completely iso - lated. furthermore, using a dc/dc converter minimizes the current drain on the battery and minimizes batter y imbalance due to electronic loading. a simple dc/dc converter is shown in figure?35 using linear technology s lt3999 dc/dc converter and a high- isolation-rated transformer. other topologies including flyback converters are possible with a suitable transformer. the npn is retained to handle the flyback converter regula - tion effects at light loads. u s ing linear technology s lt8301 isolated flyback con - verter as shown in figure?36 provides an isolated high lt c6811-1/lt c6811-2 68111fb 65 for more information www.linear.com/LTC6811-1 applications information +12v ltc6811 rbm-0512s 68111 f34 drive v reg v ? v+ c12 c0 1f 10nf 10nf 4.7 1f nsv1c201mz4 100nf 100 100 100 600z most cell connections omitted for clarity 1f +5v +v out ?v out nc +v in ?v in 6 5 4 1 2 figure?34. dc/dc converter module to power v reg 7v to 12v ph9185.011nl 1:1ct 12.1k bat54s bat54s ltc6811 lt3999 gnd 68111 f35 drive v reg v ? v+ c12 c0 1f 10nf 10nf 4.7 10f 39h 4.7f 4.7f nsv1c201mz4 100nf 100 100 100 600z most cell connections omitted for clarity 180pf 39 swa swb ilim/ss rbias v in uvlo ovlo/dc rdc rt sync 1m 49.9k 453k 17.4k 1m 261k 100nf +5v figure?35. push-pull dc/dc converter circuit to power v reg ltc6811 68111 f36 drive v reg v+ c12 c11 c10 c9 c4 c3 c2 c1 c0 v ? 1f 3.6v nsv1c201mz4 1k 100 100 3.6v 3.6v 3.6v 3.6v 3.6v 3.6v 3.6v 10f 10f 100nf 100nf ? ? bat54 bat54 lt8301 v in en/uvlo v in sw rfb r enable gnd 40h 640h some cell connections omitted for clarity figure?36. flyback converter to power v + and v reg lt c6811-1/lt c6811-2 68111fb 66 for more information www.linear.com/LTC6811-1 voltage for the v + pin. the circuit still uses the drive pin to generate v reg . this circuit minimizes the system imbalance from the lt c6811 since the supply current will only be drawn from the batteries during shutdown. it is critical to add a diode between the top monitored cell and v + so that supply current will not conduct through parasitic paths inside the ic during shutdown. internal protection and filtering internal protection features the ltc6811 incorporates various esd safeguards to ensure robust performance. an equivalent circuit showing the specific protection structures is shown in figure?37. while pins 43 to 48 have different functionality for the C1 and C2 variants, the protection structure is the same. zener-like suppressors are shown with their nominal clamp voltage, while the unmarked diodes exhibit standard pn junction behavior. filtering of cell and gpio inputs the ltc6811 uses a delta-sigma adc, which includes a delta-sigma modulator followed by a si nc3 finite impulse response (fir) digital filter. this greatly relaxes input filtering requirements. furthermore, the programmable oversampling ratio allows the user to determine the best trade-off between measurement speed and filter cutoff frequency. even with this high order low pass filter, fast transient noise can still induce some residual noise in mea - surements, especially in the faster conversion modes. this can be minimized by adding an rc low pass decoupling to each adc input, which also helps reject potentially damag - ing high energy transients. adding more than about 100 to the adc inputs begins to introduce a systematic error in the measurement, which can be improved by raising the filter capacitance or mathematically compensating in software with a calibration procedure. for situations that demand the highest level of battery voltage ripple rejec - tion, grounded capacitor filtering is recommended. this configuration has a series resistance and capacitors that decouple hf noise to v C . in systems where noise is less applications information c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 s1 c0 v ? v ? ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 gpio3 gpio2 gpio1 68111 f37 v + ltc6811 96v 24v 24v 24v 24v 30 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 29 28 27 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 12v 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 30 note: not shown are pn diodes to all other pins from pin 35 figure?37. internal esd protection structures of the ltc6811 lt c6811-1/lt c6811-2 68111fb 67 for more information www.linear.com/LTC6811-1 applications information periodic or higher oversample rates are in use, a differential capacitor filter structure is adequate. in this configuration there are series resistors to each input, but the capacitors connect between the adjacent c pins. however, the dif - ferential capacitor sections interact. as a result, the filter response is less consistent and results in less attenuation than predicted by the rc, by approximately a decade. note that the capacitors only see one cell of applied voltage (thus smaller and lower cost) and tend to distribute transient energy uniformly across the ic (reducing stress events on the internal protection structure). figure? 38 shows the two methods schematically. adc accuracy varies with r, c as shown in the typical performance curves, but error is minimized if r = 100 and c = 10nf. the gpio pins will always use a grounded capacitor configuration because the measurements are all with respect to v C . using non standard cell input filters a cell pin filter of 100 and 10nf is recommended for all applications. this filter provides the best combination of noise rejection and the total measurement error (tme) performance. in applications that use c pin rc filters larger than 100/10nf there may be additional measurement error. figure? 39a shows how both total tme and tme variation increase as the rc time constant increases. the increased error is related to the mux settling. it is possible 100nf 10nf 1f 100nf 10nf 1f figure?38. input filter structure configurations (a) cell measurement error range vs input rc values (b) cell measurement error vs input rc values (extra conversion and delay before measurement) figure?39. cell measurement tme 68111 f38 cell2 v ? c2 10nf battery v ? 100 differential capacitor filter bss308pe 33 3.3k cell1 c1 s2 s1 ltc6811 ltc6811 s2 s1 10nf 10nf 100 bss308pe 33 100 c0 3.3k cell2 v ? c2 battery v ? 100 grounded capacitor filter bss308pe 33 3.3k * cell1 c1 100 bss308pe *6.8v zeners recommended if c 100nf 33 c0 c c c 3.3k * * 100 lt c6811-1/lt c6811-2 68111fb ?8 ?7 ?4 ?3 ?2 ?1 0 1 2 cell measurement error (mv) input resistance, r () 68111 f39a input resistance, r () 100 1k 10k ?10 ?9 100 ?6 ?5 ?8 ?7 ?4 ?3 ?2 ?1 0 1 1k 2 cell measurement error (mv) 68111 f39b 10k ?10 ?9 ?6 ?5 68 for more information www.linear.com/LTC6811-1 applications information to reduce tme levels to near data sheet specifications by implementing an extra single channel conversion before issuing a standard all channel adcv command. figure? 40a shows the standard adcv command sequence. figure? 40b and figure? 40c show recommended command sequence and timing that will allow the mux to settle. the purpose of the modified procedure is to allow the mux to settle at c1/c7 before the start of the measurement cycle. the delay between the c1/c7 adcv command and the all channel adcv command is dependent on the time constant of the rc being used, the general guidance is to wait 6 between the c1/c7 adcv command and the all channel adcv com - mand. figure? 39b shows the expected tme when using the recommended command sequence. cell balancing cell balancing with internal mosfet s with passive balancing, if one cell in a series stack becomes overcharged, an s output can slowly discharge this cell by connecting it to a resistor. each s output is connected to an internal n-channel mosfet with a maximum on resistance of 25. an external resistor should be con - nected in series with these mosfets to allow most of the heat to be dissipated outside of the ltc6811 package, as illustrated in figure?41a. the internal discharge switches (mosfets) s1 through s12 can be used to passively balance cells as shown in figure?41a with balancing current of 60ma or less. bal - ancing current larger than 60ma is not recommended for (a) adcv (all cells) delay rdcva-d (b) adcv (c1/c7) delay 6 adcv (all cells) cnv time rdcva-d (c) adcv (all cells) cnv time rdcva-d adcv (c1/c7) delay 6 68111 f40 figure?40. adc command order ltc6811 68111 f41 r filter r filter c filter r discharge c(n) s(n) c(n ? 1) + r discharge bss308pe 3.3k c(n) s(n) c(n ? 1) + 1k a) internal discharge circuit b) external discharge circuit ltc6811 figure?41. internal/external discharge circuits the internal switches due to excessive die heating. when discharging cells with the internal discharge switches, the die temperature should be monitored. see the thermal shutdown section. note that the anti-aliasing filter resistor is part of the dis - charge path, so it should be removed or reduced. use of an rc for added cell voltage measurement filtering is ok but the filter resistor must remain small, typically around 10 , to reduce the effect on the balance current. lt c6811-1/lt c6811-2 68111fb 69 for more information www.linear.com/LTC6811-1 cell balancing with external transistors for applications that require balancing currents above 60ma or large cell filters, the s outputs can be used to control external transistors. the ltc6811 includes an internal pull-up pmos transistor with a 1k series resistor. the s pins can act as digital outputs suitable for driving the gate of an external mosfet as illustrated in figure? 41b. figure?38 shows external mosfet circuits that include rc filtering. for applications with very low cell voltages the pmos in figure? 41b can be replaced with a pnp. when a pnp is used, the resistor in series with the base should be reduced. choosing a discharge resistor when sizing the balancing resistor it is important to know the typical battery imbalance and the allowable time for cell balancing. in most small battery applications it is reasonable for the balancing circuitry to be able to cor - rect for a 5% soc (state of charge) error with 5 hours of balancing. for example a 5ah batter y with a 5% soc imbalance will have approximately 250mah of imbalance. using a 50ma balancing current this could be corrected in 5 hours. with a 100ma balancing current, the error would be corrected in 2.5h . in systems with very large batteries,it becomes difficult to use passive balancing to correct large soc imbalances in short periods of time. the excessive heat created during balancing generally limits the balancing current. in large capacity battery ap - plications, if short balancing times are required, an active balancing solution should be considered. when choosing a balance resistor , the following equations can be used to help determine a resistor value: b alance current = %soc_imbalance ? batterycapacity number of hours to balance b alance resistor = nominal cell voltage balance current active cell balancing applications that require 1a or greater of cell balancing current should consider implementing an active balancing system. active balancing allows for much higher balancing currents without the generation of excessive heat. active balancing also allows for energy recovery since most of the balance current will be redistributed back to the battery pack. figure?42 shows a simple active balancing implementation using linear technology s lt8584 . the lt8584 also has advanced features which can be con - trolled via the lt c6811 . see the s pin pulsing using the s control register group section and the lt ? 8584 data sheet for more details. applications information figure?42. 12-cell battery stack module with active balancing off on off on lt8584 ltc6811 battery stack monitor 2.5a average discharge module + module + module ? v + v ? /c0 bat 12 + module ? ? ? 68111 f42 2.5a average discharge module + bat 2 + module ? ? ? 2.5a average discharge module + s12 lt8584 s2 lt8584 s1 bat 1 + module ? ? ? off on lt c6811-1/lt c6811-2 68111fb 70 for more information www.linear.com/LTC6811-1 applications information discharge control during cell measurements if the discharge permitted (dcp) bit is high at the time of a cell measurement command, the s pin discharge states do not change during cell measurements. if the dcp bit is low, s pin discharge states will be disabled while the corresponding cell or adjacent cells are being measured. if using an external discharge transistor, the relatively low 1k impedance of the internal ltc6811 pmos transis - tors should allow the discharge currents to fully turn off before the cell measurement. table? 53 illustrates the adcv command with dcp = 0. in this table, off indicates that the s pin discharge is forced off irrespective of the state of the corresponding dcc[x] bit. on indicates that the s pin discharge will remain on during the measurement period if it was on prior to the measurement command. battery module balancing in some large battery systems, cells are grouped by bms ics. it is common for these groups of cells to become out of balance as compared to the other groups of cells in the battery pack. the circuit shown in figure?43 is a system to balance groups of cells connected to a single ltc6811 . this design is beneficial in combination with the individual, lower current internal discharge switches : a high module (total stack) balancing current can be implemented while lower current, lower cost, individual cell balancing is accomplished with the internal balancing switches shown in figure? 41a. top of module bottom of module ltc6811 68111 f43 v reg gpio3 v ? 1f 200 22 200 czt3055 czt2955 v + v ? figure?43. 200ma module balancer table?53. discharge control during an adcv command with dcp = 0 cell measurement periods cell calibration periods cell1/7 cell2/8 cell3/9 cell4/10 cell5/11 cell6/12 cell1/7 cell2/8 cell3/9 cell4/10 cell5/11 cell6/12 discharge pin t 0 to t 1m t 1m to t 2m t 2m to t 3m t 3m to t 4m t 4m to t 5m t 5m to t 6m t 6m to t 1c t 1c to t 2c t 2c to t 3c t 3c to t 4c t 4c to t 5c t 5c to t 6c s1 off off on on on off off off on on on off s2 off off off on on on off off off on on on s3 on off off off on on on off off off on on s4 on on off off off on on on off off off on s5 on on on off off off on on on off off off s6 off on on on off off off on on on off off s7 off off on on on off off off on on on off s8 off off off on on on off off off on on on s9 on off off off on on on off off off on on s10 on on off off off on on on off off off on s11 on on on off off off on on on off off off s12 off on on on off off off on on on off off lt c6811-1/lt c6811-2 68111fb 71 for more information www.linear.com/LTC6811-1 applications information figure?44. balancing self test circuit 68111 f44 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 v ? c0 s1 ltc6811 r b1 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b1 r b2 r b2 lt c6811-1/lt c6811-2 68111fb 72 for more information www.linear.com/LTC6811-1 applications information method to verify discharge circuits the functionality of the discharge circuits can be verified by conducting cell measurements. as shown in figure?44, a resistor between the battery cell and the source of the discharge mosfet will cause a decrease in cell voltage measurements. the amount of this measurement decrease depends on the resistor value and the mosfet on resis - tance. the following algorithm can be used in conjunction with figure?44 to verify each discharge cir cuit: 1. measure all cells with no discharging (all s outputs off) and read and store the results. 2. turn on s1 and s7. 3. measure c1-c0, c7-c6. 4. turn off s1 and s7. 5. turn on s2 and s8. 6. measure c2-c1, c8-c7. 7. turn off s2 and s8. 14. turn on s6 and s12. 15. measure c6-c5, c12-c11. 16. turn off s6 and s12. 17. read the cell voltage register groups to get the results of steps 2 thru 16. 18. compare new readings with old readings. each cell voltage reading should have decreased by a fixed percentage set by r b1 and r b2 (figure?44). the exact amount of decrease depends on the resistor values and mosfet characteristics. digital communications pec calculation the packet error code (pec) can be used to ensure that the serial data read from the ltc6811 is valid and has not been corrupted. this is a critical feature for reliable communication, particularly in environments of high noise. the ltc6811 requires that a pec be calculated for all data being read from, and written to, the ltc6811. for this reason it is important to have an efficient method for calculating the pec. the c code on page 73 provides a simple implementation of a lookup-table-derived pec calculation method. there are two functions. the first function init_pec15_table() should only be called once when the microcontroller starts and will initialize a pec15 table array called pe c15table[]. this table will be used in all future pec calculations. the pec15 table can also be hard coded into the microcon - troller rather than running the init_pec15 _table() function at startup. the pe c15 () function calculates the pec and will return the correct 15-bit pec for byte arrays of any given length. lt c6811-1/lt c6811-2 68111fb 73 for more information www.linear.com/LTC6811-1 applications information /************************************ copyright 2012 linear technology corp. (ltc) permission to freely use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies: this software is provided as is and ltc disclaims all warranties including all implied warranties of merchantability and fitness. in no event shall ltc be liable for any special, direct, indirect, or consequential damages or any damages whatsoever resulting from any use of same, including any loss of use or data or profits, whether in an action of contract, negligence or other tortuous action, arising out of or in connection with the use or performance of this software. ***********************************************************/ int16 pec15table[256]; int16 crc15_poly = 0x4599; void init_pec15_table() { for (int i = 0; i < 256; i++) { remainder = i << 7; for (int bit = 8; bit > 0; --bit) { if (remainder & 0x4000) { remainder = ((remainder << 1)); remainder = (remainder ^ crc15_poly) } else { remainder = ((remainder << 1)); } } pe c15table[i] = remainder&0xffff; } } unsigned int16 pec15 (char *data , int len) { in t16 remainder,address; remainder = 16;//pec seed for (int i = 0; i < len; i++) { address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate pec table address remainder = (remainder << 8 ) ^ pec15table[address]; } return (remainder*2) ; //the c rc15 has a 0 in the lsb so the final value must be multiplied by 2 } isospi ibias and icmp setup the ltc6811 allows the isospi links of each application to be optimized for power consumption or for noise immunity. the power and noise immunity of an isospi system is determined by the programmed i b current, which controls the isospi signaling currents. bias current i b can range from 100a to 1ma . internal circuitry scales up this bias current to create the isospi signal currents equal to 20?? ?i b . a low i b reduces the isospi power consumption in the ready and active states, while a high i b increases the amplitude of the differential signal voltage v a across the matching termination resistor, r m . the i b current is programmed by the sum of the r b1 and r b2 resistors connected between the 2v ibias pin and gnd as shown in figure?45. the receiver input threshold is set by the icmp voltage that is programmed with the resistor divider created by the r b1 and r b2 resistors. the receiver threshold will be half of the voltage present on the icmp pin. lt c6811-1/lt c6811-2 68111fb 74 for more information www.linear.com/LTC6811-1 applications information the following guidelines should be used when setting the bias current (100a to 1ma) i b and the receiver compara- tor threshold voltage v icmp /2: r m = transmission line characteristic impedance z 0 signal amplitude v a = (20 ? i b ) ? (r m /2) v tcmp (receiver comparator threshold)?=?k ? v a v icmp (voltage on icmp pin) = 2 ? v tcmp r b2 = v icmp /i b r b1 = (2/i b ) C r b2 select i b and k (signal amplitude v a to receiver compara - tor threshold ratio) according to the application: for lower power links: i b = 0.5ma and k?=?0.5 for full power links: i b = 1ma and k?=?0.5 for long links (>50m): i b = 1ma and k?=?0.25 for addressable multi-drop: i b = 1ma and k?=?0.4 for applications with little system noise, setting i b to 0.5ma is a good compromise between power consumption and noise immunity. using this i b setting with a 1: 1 transformer and r m = 100, r b1 should be set to 3.01k and r b2 set to 1k . with typical cat5 twisted pair, these settings will allow for communication up to 50m. for applications in very noisy environments or that require cables longer than 50m it is recommended to increase i b to 1ma. higher drive current compensates for the increased insertion loss in the cable and provides high noise immunity. when using cables over 50m and a transformer with a 1:1 turns ratio and r m = 100, r b1 would be 1.5k and r b2 would be 499. the maximum clock rate of an isospi link is determined by the length of the isospi cable. for cables 10 meters or less, the maximum 1mhz spi clock frequency is pos - sible. as the length of the cable increases, the maximum possible spi clock rate decreases. this dependence is a result of the increased propagation delays that can cre - ate possible timing violations. figure?46 shows how the maximum data rate reduces as the cable length increases when using a ca t5 twisted pair . cable delay affects three timing specifications: t clk , t 6 and t 7 . in the electrical characteristics table, each of these specifications is de-rated by 100ns to allow for 50ns of cable delay. for longer cables, the minimum timing pa - rameters may be calculated as shown below: t clk , t 6 and t 7 > 0.9s + 2 ? t cable (0.2m per ns) figure?45. isospi circuit r m ipa isomd v reg ima + ? + ? ibias icmp 68111 f45 ltc6811 r m r b1 r b2 r b1 r b2 ipb isomd imb ibias icmp sdi sdo sck csb sdo sdi sck cs ltc6811 twisted-pair cable with characteristic impedance r m isolation barrier (may use one or two tranformers) master ?? ?? 2v v a 2v v a figure?46. data rate vs cable length cable length (meters) 1 data rate (mbps) 1.2 0.8 0.4 0.2 1.0 0.6 0 10 68111 f46 100 cat5 assumed lt c6811-1/lt c6811-2 68111fb 75 for more information www.linear.com/LTC6811-1 applications information implementing a modular isospi daisy chain the hardware design of a daisy-chain isospi bus is identi - cal for each device in the network due to the daisy-chain point-to-point ar chitecture. the simple design as shown in figure?45 is functional, but inadequate for most designs. the termination resistor r m should be split and bypassed with a capacitor as shown in figure?47. this change provides both a differential and a common mode termination, and as such, increases the system noise immunity. the use of cables between battery modules, particularly in automotive applications, can lead to increased noise susceptibility in the communication lines. for high levels of electromagnetic interference (emc), additional filtering is recommended. the circuit example in figure?47 shows the use of common mode chokes (cmc)to add common mode noise rejection from transients on the battery lines. the use of a center tapped transformer will also provide additional noise performance. a bypass capacitor con - nected to the center tap creates a low impedance for common mode noise (f i gure? 47b). since transformers without a center tap can be less expensive, they may be preferred. in this case, the addition of a split termination resistor and a bypass capacitor (figure? 47a ) can enhance the isospi performance. large center tap capacitors greater than 10nf should be avoided as they may prevent the isospi common mode voltage from settling. common mode chokes similar to those used in ethernet or canbus applications are recommended. specific examples are provided in table?55. an important daisy chain design consideration is the number of devices in the isospi network. the length of the chain determines the serial timing and affects data latency and throughput. the maximum number of devices in an isospi daisy chain is strictly dictated by the serial timing requirements. however, it is important to note that the serial read back time, and the increased current consumption, might dictate a practical limitation. for a daisy chain, two timing considerations for proper operation dominate (see figure?25): 1. t 6 , the time between the last clock and the rising chip select, must be long enough. 2. t 5 , the time from a rising chip select to the next falling chip select (between commands), must be long enough. both t 5 and t 6 must be lengthened as the number of ltc6811 devices in the daisy chain increases. the equa - tions for these times are below: t 5 > (#devices ? 70ns) + 900ns t 6 > (#devices ? 70ns) + 950ns figure?47. daisy chain interface components isospi link xfmr isospi link ct xfmr LTC6811-1 LTC6811-1 ip im v ? 10nf 100h cmc 10nf ?? 62 62 300 300 ?? a) ip im v ? 10nf 100h cmc 10nf ?? 51 51 ?? b) 68111 f47 lt c6811-1/lt c6811-2 68111fb 76 for more information www.linear.com/LTC6811-1 applications information figure?48. daisy chain interface components on single board 10nf gndd 10nf gndd gndd gndd 10nf gndc 10nf gndc gndc gndc 10nf gndb 10nf gndb gndb 10nf gnda gndb gnda 10nf* 10nf* 1k 1k ? ? gndc 1k 1k ? ? gndb 1k 1k 1k 1k ? ? gnda gndd gndb gnda 10nf* gndc 10nf* 10nf* 10nf* 49.9 49.9 ipa ibias icmp LTC6811-1 ima 49.9 49.9 ipb imb 49.9 49.9 ipa ibias icmp LTC6811-1 ima 49.9 49.9 ipb imb 49.9 49.9 ipa ibias icmp ibias icmp LTC6811-1 v ? v ? v ? ima 49.9 49.9 ip im v ? 49.9 49.9 ipb imb * if transformer being used has a center tap, it should be bypassed with a 10nf cap 68111 f48 ltc6820 lt c6811-1/lt c6811-2 68111fb 77 for more information www.linear.com/LTC6811-1 applications information connecting multiple LTC6811-1s on the same pcb when connecting multiple ltc6811 -1 devices on the same pcb, only a single transformer is required between the ltc6811 - 1 isospi ports. the absence of the cable also reduces the noise levels on the communication lines and often only a split termination is required. figure? 48 shows an example application that has multiple LTC6811-1s on the same pcb, communicating to the bottom mcu through an ltc6820 isospi driver. if a transformer with a center tap is used, a capacitor can be added for better noise rejection. additional noise filtering can be provided with discrete common mode chokes (not shown) placed to both sides of the single transformer. on single board designs with low noise requirements, it is possible for a simplified capacitor-isolated coupling as shown in figure?49 to replace the transformer. dual zener diodes are used at each ic to clamp the common mode voltage to stay within the receivers input range. the op - tional common mode choke (cmc) provides noise rejection with symmetrically tapped termination. the 590 resistor creates a resistor divider with the termination resistors and attenuates common mode noise. the 590 value is chosen to provide the most noise attenuation while maintaining sufficient differential signal. the circuit is designed such that i b and v icmp are the same as would be used for a transformer based system with cables over 50m. figure?49. capacitive isolation coupling for LTC6811-1s on the same pcb 10nf gndb gndb gndb v reg 10nf gndb v reg 590 590 1nf 1nf 10nf gnda gnda gnda v reg 10nf gnda v reg 590 590 1nf 1nf 1nf 1nf 68111 f49 1.5k 499 ? ? 1.5k 499 ? ? ipa ibias icmp LTC6811-1 ima 100 100 3.3v 3.3v 100 100 3.3v 3.3v ipb imb v ? cmc ipa ibias icmp LTC6811-1 ima 100 100 3.3v 3.3v 100 100 3.3v 3.3v ipb imb v ? cmc lt c6811-1/lt c6811-2 68111fb 78 for more information www.linear.com/LTC6811-1 applications information connecting an mcu to an LTC6811-1 with an isospi data link the ltc6820 will convert standard 4-wire spi into a 2-wire isospi link that can communicate directly with the ltc6811 . an example is shown in figure? 50. the ltc6820 can be used in applications to provide isolation between the microcontroller and the stack of ltc6811s. the ltc6820 also enables system configurations that have the bms controller at a remote location relative to the ltc6811 devices and the battery pack. configuring the ltc6811-2 in a multiCdrop isospi link the addressing feature of the ltc6811-2 allows multiple devices to be connected to a single isospi master by dis - tributing them along one twisted pair, essentially creating a large parallel spi network. a basic multi-drop system is shown in figure? 51 ; the twisted pair is terminated only at the beginning (master) and the end of the cable. in between, the additional ltc6811-2s are connected to short stubs on the twisted pair. these stubs should be kept short, with as little capacitance as possible, to avoid degrading the termination along the isospi wiring. when an ltc6811-2 is not addressed, it will not transmit data pulses. this scheme eliminates the possibility for col - lisions since only the addressed device returns data to the master. generally , multi-drop systems are best confined to compact assemblies where they can avoid excessive isospi pulse-distortion and emc pickup. basic connection of the ltc6811-2 in a multi-drop configuration in a multi-drop isospi bus, placing the termination at the ends of the transmission line provides the best performance (with 100 typically). each of the ltc6811 isospi ports should couple to the bus with a resistor network, as shown in figure? 52a . here again, a center-tapped transformer offers the best performance and a common mode choke (cmc) increases the noise rejection further, as shown in figure?52b . figure? 52b also shows the use of an rc snub - ber at the ic connections as a means to suppress reso - nances (the ic capacitance provides sufficient out-of-band rejection). when using a non-center -tapped transformer , a virtual ct can be generated by connecting a cmc as a voltage-splitter. series resistors are recommended to decouple the ltc6811 and board parasitic capacitance from the transmission line. reducing these parasitics on the transmission line will minimize reflections. figure?50. interfacing an LTC6811-1 with a c using an ltc6820 for isolated spi control 10nf gndb gndb 10nf gnda gnda 10nf* 10nf* 10nf gndb 10nf* 1k 1k 1k 1k ? ? gnda gndb ? ? gndb gnda 49.9 49.9 49.9 49.9 ipa ibias icmp ibias icmp LTC6811-1 ima 49.9 49.9 ip im v ? ipb imb * if transformer being used has a center tap, it should be bypassed with a 10nf cap 68111 f50 ltc6820 v ? lt c6811-1/lt c6811-2 68111fb 79 for more information www.linear.com/LTC6811-1 applications information figure?51. connecting the ltc6811-2 in a multi-drop configuration figure?52. preferred isospi bus couplings for use with ltc6811-2 1.21k 806 ipa ibias isomd ima v ? v regb icmp ltc6811-2 1.21k 806 ipa ibias isomd ima v ? v rega icmp 68111 f51 ltc6811-2 1.21k 806 gndb gnda gndc gndb gnda gndc ipa ibias isomd ima v ? v regc icmp ltc6811-2 ?? ?? ?? ?? 100 1.21k 806 5k 100nf ibias icmp gnd slow mstr ip im v dd v dds en mosi miso sck cs pol pha 5v 5v 5v 5v ltc6820 100nf c sdo cs sdi sck 100 isospi bus hv xfmr ct hv xfmr 22 22 22 22 isospi bus ltc6811-2 ltc6811-2 ipa ima v ? 15pf 100h cmc 10nf ?? 100h cmc ?? 402 15pf 402 ?? a) ipa ima v ? 100h cmc 10nf ?? ?? b) 68111 f52 lt c6811-1/lt c6811-2 68111fb 80 for more information www.linear.com/LTC6811-1 applications information transformer selection guide as shown in figure?45, a transformer or pair of transform - ers isolates the isospi signals between two isospi ports. the isospi signals have programmable pulse amplitudes up to 1.6v p-p and pulse widths of 50ns and 150ns . to be able to transmit these pulses with the necessary fidelity the system requires that the transformers have primary inductances above 60h and a 1:1 turns ratio. it is also necessary to use a transformer with less than 2.5h of leakage inductance. in terms of pulse shape the primary inductance will mostly affect the pulse droop of the 50ns and 150ns pulses. if the primary inductance is too low, the pulse amplitude will begin to droop and decay over the pulse period. when the pulse droop is severe enough, the effective pulse width seen by the receiver will drop substantially, reducing noise margin. some droop is ac - ceptable as long as it is a relatively small percentage of the total pulse amplitude. the leakage inductance primarily affects the rise and fall times of the pulses. slower rise and fall times will effectively reduce the pulse width. pulse width is determined by the receiver as the time the signal is above the threshold set at the icmp pin. slow rise and fall times cut into the timing margins. generally it is best to keep pulse edges as fast as possible. when evaluating transformers, it is also worth noting the parallel winding capacitance. while transformers have very good cmrr at low frequency, this rejection will degrade at higher frequen - cies, largely due to the winding to winding capacitance. when choosing a transformer , it is best to pick one with less parallel winding capacitance when possible. table?54. recommended transformers supplier part number temperature range v working v hipot /60 s ct cmc h l w (w/leads) pins aecC q200 recommended dual t ransformers pulse hx1188fnl C40c to 85c 60v (est) 1.5kv rms l l 6.0mm 12.7mm 9.7mm 16smt C pulse hx0068anl C40c to 85c 60v (est) 1.5kv rms l l 2.1mm 12.7mm 9.7mm 16smt C pulse hm2100nl C40c to 105c 1000v 4.3kv dc C l 3.4mm 14.7mm 14.9mm 10smt l pulse hm2112znl C40c to 125c 1000v 4.3kv dc l l 4.9mm 14.8mm 14.7mm 12smt l sumida clp178-c20114 C40c to 125c 1000v (est) 3.75kv rms l l 9mm 17.5mm 15.1mm 12smt C sumida clp0612-c20115 600v rms 3.75kv rms l C 5.7mm 12.7mm 9.4mm 16smt C wurth 7490140110 C40c to 85c 250v rms 4kv rms l l 10.9mm 24.6mm 17.0mm 16smt C wurth 7490140111 0c to 70c 1000v (est) 4.5kv rms l C 8.4mm 17.1mm 15.2mm 12smt C wurth 749014018 0c to 70c 250v rms 4kv rms l l 8.4mm 17.1mm 15.2mm 12smt C halo tg110-ae050n5lf C40c to 85c/125c 60v (est) 1.5kv rms l l 6.4mm 12.7mm 9.5mm 16smt l recommended single transformers pulse pe-68386nl C40c to 130c 60v (est) 1.5kv dc C C 2.5mm 6.7mm 8.6mm 6smt C pulse hm2101nl C40c to 105c 1000v 4.3kv dc C l 5.7mm 7.6mm 9.3mm 6smt l pulse hm2113znl C40c to 125c 1600v 4.3kv dc l l 3.5mm 9mm 15.5mm 6smt l wurth 750340848 C40c to 105c 250v 3kv rms C C 2.2mm 4.4mm 9.1mm 4smt C halo tgr04-6506v6lf C40c to 125c 300v 3kv rms l C 10mm 9.5mm 12.1mm 6smt C halo tgr04-a6506na6nl C40c to 125c 300v 3kv rms l C 9.4mm 8.9mm 12.1mm 6smt l halo tdr04-a550allf C40c to 105c 1000v 5kv rms l C 6.4mm 8.9mm 16.6mm 6th l tdk alt4532v-201-t001 C40c to 105c 60v (est) ~1kv l C 2.9mm 3.2mm 4.5mm 6smt l halo tdr04-a550allf C40c to 105c 1000v 5kv rms l C 6.4mm 8.9mm 16.6mm 6th l sumida ceeh96bnp-ltc6804/11 C40c to 125c 600v 2.5kv rms C C 7mm 9.2mm 12.0mm 4smt ? sumida cep99np-ltc6804 C40c to 125c 600v 2.5kv rms l C 10mm 9.2mm 12.0mm 8smt C sumida esmit-4180/a C40c to 105c 250v rms 3kv rms C C 3.5mm 5.2mm 9.1mm 4smt l tdk vgt10/9ee-204s2p4 C40c to 125c 250v (est) 2.8kv rms l C 10.6mm 10.4mm 12.7mm 8smt ? lt c6811-1/lt c6811-2 68111fb 81 for more information www.linear.com/LTC6811-1 applications information when choosing a transformer, it is equally important to pick a part that has an adequate isolation rating for the application. the working voltage rating of a transformer is a key spec when selecting a part for an application. interconnecting daisy-chain links between LTC6811-1 devices see <60v stress in typical applications; ordinary pulse and lan type transformers will suffice. multi-drop connections and connections to the ltc6820, in general, may need much higher working voltage ratings for good long-term reliability. usually, matching the working voltage to the voltage of the entire battery stack is conservative. unfortunately, transformer vendors will often only specify one-second hv testing, and this is not equal to the long-term (permanent) rating of the part. for example, according to most safety standards a 1.5kv rated transformer is expected to handle 230v continuously, and a 3kv device is capable of 1100v long-term, though manufacturers may not always certify to those levels (refer to actual vendor data for specifics). usually, the higher voltage transformers are called high-isolation or reinforced insulation types by the suppliers. table?54 shows a list of transformers that have been evaluated in isospi links. in most applications a common mode choke is also necessary for noise rejection. table?55 includes a list of suitable cmcs if the cmc is not already integrated into the transformer being used. isospi layout guidelines layout of the isospi signal lines also plays a significant role in maximizing the noise immunity of a data link. the following layout guidelines are recommended: 1. the transformer should be placed as close to the isospi cable connector as possible. the distance should be kept less than 2cm. the ltc6811 should be placed close to but at least 1cm to 2cm away from the transformer to help isolate the ic from magnetic field coupling. 2. a v C ground plane should not extend under the trans - former, the isospi connector or in between the trans - former and the connector. 3. the isospi signal traces should be as direct as possible while isolated from adjacent cir cuitr y by ground metal or space. no traces should cross the isospi signal lines, unless separated by a ground plane on an inner layer. system supply current the ltc6811 has various supply current specifications for the different states of operation. the average supply current depends on the control loop in the system. it is necessary to know which commands are being executed table?56. daisy chain serial time equations command type cmd bytes + cmd pec data bytes + data pec per ic total bits communica tion time read 4 8 (4 + (8 ? #ics)) ? 8 total bits ? clock period write 4 8 (4 + (8 ? #ics)) ? 8 total bits ? clock period operation 4 0 4 ? 8 = 32 32 ? clock period table?57. multi-drop serial time equations command type cmd bytes + cmd pec data bytes + data pec per ic total bits communica tion time read 4 8 ((4 + 8) ? #ics) ? 8 total bits ? clock period write 4 8 ((4 + 8) ? #ics) ? 8 total bits ? clock period operation 4 0 4 ? 8 = 32 32 ? clock period table?55. recommended common mode chokes manufacturer part number tdk act45b-101-2p murata dlw43sh101xk2 lt c6811-1/lt c6811-2 68111fb 82 for more information www.linear.com/LTC6811-1 applications information each control loop cycle, and the duration of the control loop cycle. from this information it is possible to determine the percentage of time the ltc6811 is in the measure state versus the low power sleep state. the amount of isospi or spi communication will also affect the average supply current. calculating serial throughput for any given ltc6811 the calculation to determine com - munication time is simple: it is the number of bits in the transmission multiplied by the spi clock period being used. the control protocol of the ltc6811 is very uniform so almost all commands can be categorized as a write, read or an operation. table?55, table?56 and table?57 can be used to determine the number of bits in a given ltc6811 command. table? 56 can be used for daisy chains and table?57 for multi-drop networks. enhanced applications using the ltc6811 with fewer than 12 cells internally the 12 cell inputs monitored by the ltc6811 are split into two groups of six cells and are measured using two internal multiplexers and two adcs. to optimize mea - surement synchronization in applications with fewer than twelve cells, the unused c pins may be equally distributed between the top of the second mux ( c12 ) and the top of the first mux (c6 ). see figure?53. if there are an odd number of cells being measured, the top mux should have fewer cells connected. the unused cell inputs should be tied to the other unused inputs on the same mux and then connected to the battery stack through a 100 resistor. the unused inputs will result in a reading of 0.0v for those cells. it is also acceptable to connect cells in the conventional sequence with all unused inputs at the top left open-circuit. figure?53. cell connection schemes for 5 to 12 cells v + c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 drive v reg v ? c0 ltc6811 68111 f53 b1 b2 b3 b4 b5 b1 b2 b3 b4 b5 5 cells 6 cells 7 cells 8 cells 9 cells 10 cells 11 cells b6 b1 b2 b3 b4 b5 b6 b7 b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 b4 b5 b6 b7 b8 b9 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 12 cells 100 100 100 100 100 100 100 100 100 100 100 100 100 10 lt c6811-1/lt c6811-2 68111fb 83 for more information www.linear.com/LTC6811-1 applications information monitoring fewer than 5 cells in applications using four cells or fewer, the v + must be provided by a separate supply to guarantee that the ltc6811 will operate over the cells entire voltage range. figure?54 shows an application circuit to monitor 4 cells. the lt8301 is used to generate an isolated 18v supply. it is important that the converter produces a v + that is at a higher potential than the cell stack potential. in this case an 18v supply will allow the ltc6811 to operate with four cell voltages between 2v and 4.5v. current measurement with a hall-effect sensor the ltc6811 auxiliary adc inputs (gpio pins) may be used for any analog signal, including active sensors with 0v to 5v analog outputs. for battery current measurements, hall-effect sensors provide an isolated, low power solution. figure?55 shows schematically a typical hall-effect sen - sor that produces two outputs that proportion to the v cc provided. the sensor in the figure has two bidirectional outputs centered at half of v cc , ch1 is a 0a to 50a low range and ch2 is a 0a to 200a high range. the sensor is figure?54. powering the ltc6811 when monitoring 4 cells ltc6811 68111 f54 drive v reg v+ c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 v ? 1f 3.6v 3.6v 3.6v 3.6v nsv1c201mz4 1k 100 100 10f 10f 100nf 100nf ? ? bat54 bat54 lt8301 v in en/uvlo v in 2.7v to 36v sw rfb r enable gnd 40h 40h cmdz5248b cmhd448 lt c6811-1/lt c6811-2 68111fb 84 for more information www.linear.com/LTC6811-1 applications information powered from a 5v source and produces analog outputs that are connected to gpio pins or inputs of the mux ap - plication shown in figure?58. the use of gpio1 and gpio2 as the adc inputs has the possibility of being digitized within the same conversion sequence as the cell inputs (using the adcv ax command), thus synchronizing cell voltage and cell current measurements. low side current sense many batter y current sense applications require a bidirec - tional measurement that has both high accuracy and a wide dynamic range. hall-effect sensors often have 2 outputs with different ranges to accommodate this requirement. for current sense solutions, using a small sense resistor shunt and a programmable gain amplifier provides a wide dynamic rage solution. linear technology s ltc6915 digi - tally programmable instrumentation amplifier is a good choice for this application because of its low 10v offset and virtually no temperature coefficient. this allows the amplifier to work well with shunts of 100? or greater. figure?56 shows the ltc6915 configured to monitor bidi - rectional current on a low side shunt. because of the low side ar chitecture, a charge pump is needed to provide a negative rail for the amplifier to measure the shunt current during battery discharge. figure?55. interfacing a typical hall-effect battery current sensor to auxiliary adc inputs 68111 f55 lem dhab ch2 analog gpio2 v cc 5v gnd analog_com v ? ch1 analog0 gpio1 a b c d figure?56. low side current sense ?5v +5v ltc6811 ltc6915 68111 f54 gpio1 v ref2 v reg gpio3 gpio4 gpio5 v ? in+ in? 3.6v 3.6v 3.6v 3.6v 10k 100 10k 10k out sense ref v + shdn cs d in clk d gnd serial 1f 10f 1f 1f 1f 10nf ltc3261 v in en r t v out mode gnd v reg v ? c+ c? 100 lt c6811-1/lt c6811-2 68111fb 85 for more information www.linear.com/LTC6811-1 applications information reading external temperature probes figure?57 shows the typical biasing circuit for a negative- temperature-coefficient (ntc) thermistor. the 10k at 25c is the most popular sensor value and the v ref2 output stage is designed to provide the current required to bias several of these probes. the biasing resistor is selected to correspond to the ntc value so the circuit will provide 1.5v at 25c (v ref2 is 3v nominal). the overall circuit response is approximately C1%/c in the range of typical cell temperatures, as shown in the chart of figure?57. expanding the number of auxiliary measurements the ltc6811 has five gpio pins that can be used as adc inputs. in applications that need to measure more than five signals a multiplexer (mux) circuit can be implemented to expand the analog measurements to sixteen different signals (figure? 58). the gpio1 adc input is used for measurement and mux control is provided by the i 2 c port on gpio 4 and 5. the buffer amplifier was selected for fast settling and will increase the usable throughput rate. figure?57. typical temperature probe circuit and relative output figure?58. mux circuit supports sixteen additional analog measurements temperature (c) ?40 0 v tempx (% v ref2 ) 100 80 60 40 20 90 70 50 30 10 0 ?20 20 6040 80 68111 f55 10k ntc 10k at 25c v ? v ref2 v temp s0 s1 s2 s3 s4 s5 s6 s7 v cc scl sda a0 a1 gnd v ee d o analog1 analog2 analog3 analog4 analog5 analog6 analog7 analog8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1380 s0 s1 s2 s3 s4 s5 s6 s7 v cc scl sda a0 a1 gnd v ee d o analog9 analog10 analog11 analog12 analog13 analog14 analog15 analog16 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1380 3 27 31 32 33 37 5 1f 10nf 68111 f57 v reg gpio5(scl) gpio4(sda) v ? gpio1 ltc6811 4.7k 4.7k 1 2 4 ? + ltc6255 100 analog inputs: 0.04v to 4.5v lt c6811-1/lt c6811-2 68111fb 86 for more information www.linear.com/LTC6811-1 package description please refer to http://www.linear.com/product/LTC6811-1#packaging for the most recent package drawings. 0.10 ? 0.25 (.004 ? .010) 0 ? 8 g48 (ssop) 0814 rev a seating plane 0.55 ? 0.95** (.022 ? .037) 1.25 (.0492) ref 5.00 ? 5.60* (.197 ? .221) 7.40 ? 8.20 (.291 ? .323) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 13 4445464748 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 32 12.50 ? 13.10* (.492 ? .516) 2.0 (.079) max 1.65 ? 1.85 (.065 ? .073) 0.05 (.002) min 0.50 (.01968) bsc 0.20 ? 0.315 ? (.008 ? .0124) typ millimeters (inches) dimensions do not include mold flash or protrusions, but do include mold mismatch and are measured at the parting line. mold flash shall not exceed .15mm per side length of lead for solderring to a substrate the maximum dimension does not include dambar protrusions. dambar protrusions do not exceed 0.13mm per side * ** ? note: 1.drawing is not a jedec outline 2. controlling dimension: millimeters 3. dimensions are in 4. drawing not to scale 5. formed leads shall be planar with respect to one another within 0.08mm at seating plane 0.25 0.05 parting line 0.50 bsc 5.3 ? 5.7 7.8 ? 8.2 recommended solder pad layout apply solder mask to areas that are not soldered 1.25 0.12 g package 48-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1887 rev a) g package 48-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1887 rev a) lt c6811-1/lt c6811-2 68111fb 87 for more information www.linear.com/LTC6811-1 revision history rev date description page number a 05/17 t skew2 specification correction: min = 211s t 5gov specification correction: min = 0.6s, max = 0.82s t 6gov specification correction: min = 0.6s, max = 1.05s typical performance characteristics curve isospi comparator threshold gain (port a/port b) vs i bias current renamed isospi comparator threshold gain (port a/port b) vs receiver common mode clarification to the impact statement of the absolute maximum spefications for the comparison of the ltc6811 restriction vs ltc6804 corrections to table 1. core supply current: standby, i reg(core) = 40a; refup, i vp = 550a, i reg(core) = 450a; measure, i vp = 550a corrections to the overlap cell measurement (adol command) section: after an adol command, the result from adc2 is placed in cell voltage register group c and the result from adc1 is placed in cell voltage register group c. correction to table 52. memory bit descriptions: dten description updated to include read only. addition of the using non-standard cell input filters section and figures 38 through 40. all figures beginning with figure 38 and above renumbered. table 54. recommended transformers updated. 7 9 9 15 19 21 31 62 67 67- 88 80 b 08/17 updated drive output voltage specifications 7 lt c6811-1/lt c6811-2 68111fb 88 for more information www.linear.com/LTC6811-1 ? linear technology corporation 2016 lt 0817 rev b ? printed in usa www.linear.com/LTC6811-1 related parts typical application part number description comments ltc6801 12-cell battery fault monitor monitors individual battery cells for undervoltage or overvoltage. companion to ltc6802, ltc6803, ltc6804, ltc6811 ltc6802 precision 12-cell multicell battery monitor 1 st generation: superseded by the ltc6804 and ltc6803 for new designs ltc6803 precision 12-cell multicell battery monitor 2 nd generation: functionally enhanced and pin compatible to the ltc6802 ltc6804 precision 12-cell multicell battery monitor 3 rd generation: 0.025% measurement accuracy, built-in isolated communication (isospi). superseded by the pin compatible ltc6811 ltc6820 isolated bidirectional communications interface for spi provides an isolated interface for spi communication up to 100 meters, using a twisted pair. companion to the ltc6804 and ltc6811 ltc3300 bidirectional multicell battery balancer synchronous flyback, support 6 cells in series, 10a balancing current, 92% efficiency lt8584 monolithic active cell balancer single cell, monolithic flyback dc/dc converter, integrated 6a, 50v power switch, ssop-16 68111 ta02 v + c12 s12 c11 s11 c10 s10 c9 s9 c8 s8 c7 s7 c6 s6 c5 s5 c4 s4 c3 s3 c2 s2 c1 ipb imb icmp ibias sdo (nc) sdi (nc) sck (ipa) csb (ima) isomd wdt drive v reg dten v ref1 v ref2 gpio5 gpio4 v ? v ? gpio3 gpio2 gpio1 c0 s1 LTC6811-1 10 7 6 8 9 11 isospia ? isospi port a tg110-ae050n5* isospia + 2 1 1k 1k cell2 3.6v 10nf 100 bss308pe 33 3.3k cell1 3.6v cell3 3.6v 10nf 100 bss308pe 33 3.3k + + + cell12 3.6v 10nf 100 bss308pe 33 100 100 3.3k cell11 3.6v 100 cell3 to cell11 circuits 1f 100nf 100nf 1f 1f 100 15 2 1 3 14 16 isospib ? isospi port b isospib + 2 1 100 10nf *the part shown is a dual transformer with built-in common mode chokes 10nf ?? ?? + + nsv1c201mz4 basic 12-cell monitor with isospi daisy chain lt c6811-1/lt c6811-2 68111fb |
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